40 lines
711 B
Verilog
40 lines
711 B
Verilog
// Check that break and continue are supported in constant functions in for
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// loops
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module test;
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function automatic integer f1(integer x);
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integer j = 0;
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for (integer i = 0; i < 10; i++) begin
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if (i >= x) begin
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break;
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end
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j++;
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end
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return j;
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endfunction
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function automatic integer f2(integer x);
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integer j = 0;
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for (integer i = 0; i < x; i++) begin
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if (i % 2 == 0) begin
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continue;
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end
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j++;
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end
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return j;
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endfunction
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reg [f1(3):0] x;
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reg [f2(6):0] y;
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initial begin
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if ($bits(x) === 4 && $bits(y) === 4) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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