17 lines
366 B
Verilog
17 lines
366 B
Verilog
module test(_clock);
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// --- params ---
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input _clock;
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// --- vars ---
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reg [15:0] m;
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reg [15:0] a;
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// --- body ---
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always @ (posedge _clock)
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begin
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m = 1;
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a[15*m] = 1; // accepted by icarus, but thought that verilog expected a const-expression
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a[15:0] = 1; // ok
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a[15*m:0] = 1; // causes error, but not sure if this is legal syntax
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end
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endmodule // test
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