50 lines
1.2 KiB
ReStructuredText
50 lines
1.2 KiB
ReStructuredText
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The sizer Code Analyzer (-tvvp)
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===============================
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The sizer target does not generate any code. Instead it will print statistics about the Verilog code.
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It is important to synthesize the Verilog code before invoking the sizer. This can be done with the `-S` flag passed to iverilog. Note, that behavioral code can not be synthesized and will generate a warning when passed to the sizer.
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Example command::
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% iverilog -o sizer.txt -tsizer -S -s top input.v
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With this example code:
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.. code-block:: verilog
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module top (
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input clock,
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input reset,
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output blink
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);
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reg out;
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always @(posedge clock) begin
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if (reset) begin
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out = 1'b0;
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end else begin
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out <= !out;
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end
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end
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assign blink = out;
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endmodule
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The resulting `sizer.txt` will contain::
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**** module/scope: top
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Flip-Flops : 1
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Logic Gates : 3
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MUX[2]: 1 slices
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LOG[13]: 1 unaccounted
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LOG[14]: 1 unaccounted
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**** TOTALS
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Flip-Flops : 1
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Logic Gates : 3
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MUX[2]: 1 slices
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LOG[13]: 1 unaccounted
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LOG[14]: 1 unaccounted
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