mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-29 01:03:29 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
240 lines
7.8 KiB
Perl
Executable File
240 lines
7.8 KiB
Perl
Executable File
#!/usr/bin/env perl
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#
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# Regression script for VHDL output. Based on vvp_reg.pl.
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#
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# This script is based on code with the following Copyright.
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#
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# Copyright (c) 1999-2020 Guy Hutchison ([email protected])
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#
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# This source code is free software; you can redistribute it
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# and/or modify it in source code form under the terms of the GNU
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# General Public License as published by the Free Software
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# Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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use lib './perl-lib';
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use RegressionList;
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use Diff;
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use Reporting;
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use Environment;
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#
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# Main script
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#
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&open_report_file('vhdl_regression_report.txt');
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my ($suffix, $strict, $with_valg, $force_sv) = &get_args;
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my $ver = &get_ivl_version($suffix);
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my $msg = $with_valg ? " (with valgrind)" : "";
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&print_rpt("Running VHDL tests for Icarus Verilog version: $ver$msg.\n");
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&print_rpt("-" x 70 . "\n");
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if ($#ARGV != -1) {
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my $regress_fn = &get_regress_fn;
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&read_regression_list($regress_fn, $ver, $force_sv, "");
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} else {
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&read_regression_list("vhdl_regress.list", $ver, $force_sv, "");
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}
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&execute_regression($suffix, $with_valg);
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&close_report_file;
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#
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# execute_regression sequentially compiles and executes each test in
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# the regression. It then checks that the output matches the gold file.
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#
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sub execute_regression {
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my $sfx = shift(@_);
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my $with_valg = shift(@_);
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my ($tname, $total, $passed, $failed, $expected_fail, $not_impl,
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$len, $cmd, $diff_file, $outfile, $unit);
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$total = 0;
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$passed = 0;
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$failed = 0;
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$expected_fail = 0;
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$not_impl = 0;
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$len = 0;
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# Check for the VHDL output directory
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mkdir 'vhdl' unless (-d 'vhdl');
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foreach $tname (@testlist) {
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$len = length($tname) if (length($tname) > $len);
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}
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foreach $tname (@testlist) {
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next if ($tname eq ""); # Skip test that have been replaced.
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$total++;
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&print_rpt(sprintf("%${len}s: ", $tname));
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if ($diff{$tname} ne "" and -e $diff{$tname}) {
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unlink $diff{$tname} or
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die "Error: unable to remove old diff file $diff{$tname}.\n";
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}
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if (-e "log/$tname.log") {
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unlink "log/$tname.log" or
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die "Error: unable to remove old log file log/$tname.log.\n";
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}
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if ($testtype{$tname} eq "NI") {
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&print_rpt("Not Implemented.\n");
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$not_impl++;
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next;
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}
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# Store all the output in the vhdl subdirectory for debugging
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$outfile = "vhdl/$tname.vhd";
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#
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# Build up the iverilog command line and run it.
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#
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$cmd = $with_valg ? "valgrind --trace-children=yes " : "";
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$cmd .= "iverilog$sfx -t vhdl -o $outfile $args{$tname}";
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$cmd .= " -s $testmod{$tname}" if ($testmod{$tname} ne "");
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$cmd .= " ./$srcpath{$tname}/$tname.v > log/$tname.log 2>&1";
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#print "$cmd\n";
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if (system("$cmd")) {
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if ($testtype{$tname} eq "CE") {
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# Check if the system command core dumped!
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if ($? >> 8 & 128) {
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&print_rpt("==> Failed - CE (core dump).\n");
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$failed++;
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} else {
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&print_rpt("Passed - CE.\n");
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$passed++;
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}
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next;
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}
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# Check the log file for an un-translatable construct error
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# We report this separately so we can distinguish between
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# expected and unexpected failures
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$cmd = "grep -q -i -E '(no vhdl translation|cannot be translated)' log/$tname.log";
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if (system($cmd) == 0) {
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&print_rpt("==> Failed - No VHDL translation.\n");
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$not_impl++;
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next;
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}
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else {
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&print_rpt("==> Failed - running iverilog.\n");
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$failed++;
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next;
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}
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}
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#
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# Compile the output with GHDL
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#
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$cmd = "(cd vhdl ; ghdl -a $tname.vhd) >> log/$tname.log 2>&1";
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#print "$cmd\n";
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if (system("$cmd")) {
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if ($testtype{$tname} eq "CE") {
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# Check if the system command core dumped!
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if ($? >> 8 & 128) {
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&print_rpt("==> Failed - CE (core dump).\n");
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$failed++;
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} else {
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&print_rpt("Passed - CE.\n");
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$passed++;
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}
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next;
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}
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&print_rpt("==> Failed - running ghdl.\n");
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$failed++;
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next;
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}
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# The CO test type now includes compilation of the VHDL
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if ($testtype{$tname} eq "CO") {
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&print_rpt("Passed - CO.\n");
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$passed++;
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next;
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}
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# Try to guess the name of the primary VHDL unit
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# ghdl -f lists all the units in a file: take the first one
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($unit) = `ghdl -f $outfile` =~ /^entity (\w+)/;
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unless ($unit) {
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&print_rpt("==> Failed -- cannot determine primary VHDL unit.\n");
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$failed++;
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next;
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}
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#print "primary unit is $unit\n";
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# Elaborate the primary unit to produce and executable
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# Could elaborate and run in a single step, but this should
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# provide better error detection.
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$cmd = "(cd vhdl ; ghdl -e $unit) >> log/$tname.log 2>&1";
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#print "$cmd\n";
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if (system($cmd)) {
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&print_rpt("==> Failed - running ghdl elaboration step.\n");
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$failed++;
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next;
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}
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# Finally, run the exectutable
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$cmd = "(cd vhdl ; ghdl -r $unit --stop-delta=10000) >> log/$tname.log 2>&1";
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#print "$cmd\n";
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if (system($cmd)) {
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if ($testtype{$tname} eq "RE") {
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&print_rpt("Passed - RE.\n");
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$passed++;
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next;
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}
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else {
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# If the log contains `SIMULATION FINISHED' then
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# this is OK
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$cmd = "grep -q 'SIMULATION FINISHED' log/$tname.log";
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if (system($cmd)) {
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&print_rpt("==> Failed - simulating VHDL.\n");
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$failed++;
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next;
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}
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}
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}
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if ($diff{$tname} ne "") {
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$diff_file = $diff{$tname}
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} else {
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$diff_file = "log/$tname.log";
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}
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# print "diff $gold{$tname}, $diff_file, $offset{$tname}\n";
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if (diff($gold{$tname}, $diff_file, $offset{$tname})) {
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if ($testtype{$tname} eq "EF") {
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&print_rpt("Passed - expected fail.\n");
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$expected_fail++;
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next;
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}
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&print_rpt("==> Failed - output does not match gold file.\n");
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$failed++;
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next;
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}
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&print_rpt("Passed.\n");
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$passed++;
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} continue {
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if ($tname ne "") {
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# Remove GHDL temporary files
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my $tmpfiles = './vhdl/*.o ./vhdl/work-obj93.cf';
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$tmpfiles .= " ./vhdl/$unit" if $unit;
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system("rm -f $tmpfiles") and
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die "Error: failed to remove temporary files.\n";
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}
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}
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&print_rpt("=" x 70 . "\n");
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&print_rpt("Test results:\n Total=$total, Passed=$passed, Failed=$failed,".
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" Not Implemented=$not_impl, Expected Fail=$expected_fail\n");
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}
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