iverilog/vhdlpp
Stephen Williams 04b239a5fb Flesh out VHDL parser engine.
Add enough rules to parse a simple VHDL program:
  Parse library and use clauses,
  Parse entity declarations, and
  Parse architecture bodies.

Add some parser infrastructure:
  Handle syntax errors with useful error messages,
  Include file name and line numbers in parse errors,
  Add some parser debug aids.
2011-01-18 17:03:51 -08:00
..
Makefile.in Introduce shell of vhdlpp program. 2011-01-18 17:03:51 -08:00
compiler.h Introduce shell of vhdlpp program. 2011-01-18 17:03:51 -08:00
lexor.lex Flesh out VHDL parser engine. 2011-01-18 17:03:51 -08:00
lexor_keyword.gperf Flesh out VHDL parser engine. 2011-01-18 17:03:51 -08:00
main.cc Flesh out VHDL parser engine. 2011-01-18 17:03:51 -08:00
parse.y Flesh out VHDL parser engine. 2011-01-18 17:03:51 -08:00
parse_api.h Flesh out VHDL parser engine. 2011-01-18 17:03:51 -08:00
vhdlpp_config.h.in Introduce shell of vhdlpp program. 2011-01-18 17:03:51 -08:00