Files
iverilog/tgt-vvp
Cary R e362a86b16 Fix procedural concatenation/repetition problems
This patch evaluates the whole concatenation expression and
makes the concatenation padding sign aware. This is needed
when $signed({...}) is passed as an argument.

A repetition is just N copies of the base expression not N
evaluations of the base expression. This is only a problem
when functions have side effects. It's also faster to copy.
The evaluation must also be done when the replication count
is zero (see 1364-2005).
2009-07-28 19:45:26 -07:00
..
2008-09-29 18:06:47 -07:00
2008-09-29 18:06:47 -07:00
2008-09-29 18:06:47 -07:00

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.


GENERAL FUNCTOR WEB STRUCTURE

The net of gates, signals and resolvers is formed from the input
design. The basic structure is wrapped around the nexus, which is
represented by the ivl_nexus_t.

Each nexus represents a resolved value. The input of the nexus is fed
by a single driver. If the nexus in the design has multiple drivers,
the drivers are first fed into a resolver (or a tree of resolvers) to
form a single output that is the nexus.

The nexus, then, feeds its output to the inputs of other gates, or to
the .net objects in the design.