41 lines
707 B
Verilog
41 lines
707 B
Verilog
// This tests a concrete interface-typed module port without an explicit
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// modport restriction.
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//
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// This file is placed into the Public Domain, for any use, without
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// warranty.
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module test;
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logic [7:0] lhs;
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logic [7:0] rhs;
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bus_if bus();
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add_if dut(.bus(bus));
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assign bus.lhs = lhs;
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assign bus.rhs = rhs;
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initial begin
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lhs = 8'd9;
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rhs = 8'd4;
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#1;
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if (bus.sum !== 9'd13) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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module add_if(
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bus_if bus
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);
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assign bus.sum = bus.lhs + bus.rhs;
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endmodule
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interface bus_if ();
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logic [7:0] lhs;
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logic [7:0] rhs;
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logic [8:0] sum;
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endinterface
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