48 lines
902 B
Verilog
48 lines
902 B
Verilog
// This tests a SystemVerilog interface-typed module port with an
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// explicit modport and a named actual interface instance connection.
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//
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// This file is placed into the Public Domain, for any use, without
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// warranty.
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module test;
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logic [7:0] lhs;
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logic [7:0] rhs;
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bus_if bus();
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add_if dut(.bus(bus));
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assign bus.lhs = lhs;
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assign bus.rhs = rhs;
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initial begin
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lhs = 8'd5;
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rhs = 8'd7;
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#1;
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if (bus.sum !== 9'd12) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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interface bus_if #(parameter WIDTH = 8) ();
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logic [WIDTH-1:0] lhs;
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logic [WIDTH-1:0] rhs;
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logic [WIDTH:0] sum;
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modport consumer(
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input lhs,
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input rhs,
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output sum
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);
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endinterface
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module add_if #(parameter WIDTH = 8) (
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bus_if.consumer bus
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);
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assign bus.sum = bus.lhs + bus.rhs;
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endmodule
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