47 lines
1.0 KiB
Verilog
47 lines
1.0 KiB
Verilog
// This tests a one-dimensional interface formal array connected to a
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// whole interface instance array, then indexed inside the receiving
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// module.
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interface bus_if ();
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logic [7:0] value;
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modport producer(output value);
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modport consumer(input value);
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endinterface
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module drive(input [7:0] val, bus_if.producer bus);
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assign bus.value = val;
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endmodule
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module sample(output [7:0] y, bus_if.consumer bus);
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assign y = bus.value;
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endmodule
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module child_array(output [7:0] y0, output [7:0] y1,
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bus_if.consumer bus[2]);
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sample c0(.y(y0), .bus(bus[0]));
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sample c1(.y(y1), .bus(bus[1]));
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endmodule
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module test;
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bus_if buses[2]();
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wire [7:0] y0;
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wire [7:0] y1;
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drive d0(8'd21, buses[0]);
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drive d1(8'd42, buses[1]);
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child_array dut(.bus(buses), .y0(y0), .y1(y1));
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initial begin
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#1;
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if (y0 !== 8'd21) begin
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$display("FAILED: y0=%0d", y0);
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$finish;
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end
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if (y1 !== 8'd42) begin
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$display("FAILED: y1=%0d", y1);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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