77 lines
2.8 KiB
Verilog
77 lines
2.8 KiB
Verilog
/*
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* Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* IVL should generate an AND gate, and should make an OBUF and two
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* IBUF objects, along with the PAD objects.
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*
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* To compile this for XNF, try a command like this:
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*
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* iverilog -txnf -ppart=XC4010XLPQ160 -ooutff.xnf -pncf=outff.ncf outff.v
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*
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* That command causes an outff.xnf and outff.ncf file to be created.
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* Next, make the outff.ngd file with the command:
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*
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* xnf2ngd -l xilinxun -u outff.xnf outff.ngo
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* ngdbuild outff.ngo outff.ngd
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*
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* Finally, map the file to fully render it in the target part. The
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* par command is the step that actually optimizes the design and tries
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* to meet timing constraints.
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*
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* map -o map.ncd outff.ngd
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* par -w map.ncd outff.ncd
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*
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* At this point, you can use the FPGA Editor to edit the outff.ncd
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* file to see that the AND gate is in a CLB and the IOB for pin 150
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* has its flip-flop in use, and that gbuf is a global buffer.
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*/
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module main;
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wire clk, iclk;
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wire i0, i1;
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wire out;
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reg o0;
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// This simple logic gate get turned into a function unit.
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// The par program will map this into a CLB F or G unit.
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and (out, i0, i1);
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// This creates a global clock buffer. Notice how I attach an
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// attribute to the named gate to force it to be mapped to the
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// desired XNF device. This device will not be pulled into the
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// IOB associated with iclk because of the attribute.
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buf gbuf(clk, iclk);
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$attribute(gbuf, "XNF-LCA", "GCLK:O,I");
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// This is mapped to a DFF. Since o0 is connected to a PAD, it
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// is turned into a OUTFF so that it get placed into an IOB.
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always @(posedge clk) o0 = out;
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// These attribute commands assign pins to the listed wires.
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// This can be done to wires and registers, as internally both
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// are treated as named signals.
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$attribute(o0, "PAD", "o150");
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$attribute(i0, "PAD", "i152");
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$attribute(i1, "PAD", "i153");
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$attribute(iclk,"PAD", "i154");
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endmodule /* main */
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