40 lines
1.3 KiB
Plaintext
40 lines
1.3 KiB
Plaintext
:vpi_module "system";
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; Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
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;
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; This source code is free software; you can redistribute it
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; and/or modify it in source code form under the terms of the GNU
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; General Public License as published by the Free Software
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; Foundation; either version 2 of the License, or (at your option)
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; any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, write to the Free Software
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; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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; This example is similar to the code that the following Verilog program
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; would make:
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;
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; module main;
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; initial $display("Hello, World.");
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; endmodule
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;
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; This tests that a simple %vpi_call works properly. This is very nearly
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; the mode trivial VVP source file that can generate any output.
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main .scope module, "main";
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code
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%vpi_call 0 0 "$display", "Hello, World.";
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%end;
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.thread code;
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:file_names 2;
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"N/A";
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"<interactive>";
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