1004 lines
21 KiB
C++
1004 lines
21 KiB
C++
/*
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* Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "arith.h"
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# include "schedule.h"
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# include <limits.h>
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# include <iostream>
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# include <assert.h>
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# include <stdlib.h>
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#ifdef HAVE_MALLOC_H
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# include <malloc.h>
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#endif
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# include <math.h>
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vvp_arith_::vvp_arith_(unsigned wid)
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: wid_(wid), x_val_(wid)
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{
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for (unsigned idx = 0 ; idx < wid ; idx += 1)
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x_val_.set_bit(idx, BIT4_X);
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op_a_ = x_val_;
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op_b_ = x_val_;
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}
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void vvp_arith_::dispatch_operand_(vvp_net_ptr_t ptr, vvp_vector4_t bit)
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{
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unsigned port = ptr.port();
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switch (port) {
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case 0:
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op_a_ = bit;
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break;
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case 1:
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op_b_ = bit;
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break;
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default:
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fprintf(stderr, "Unsupported port type %d.\n", port);
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assert(0);
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}
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}
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vvp_arith_abs::vvp_arith_abs()
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{
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}
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vvp_arith_abs::~vvp_arith_abs()
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{
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}
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void vvp_arith_abs::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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vvp_vector4_t out (bit.size(), BIT4_0);;
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vvp_bit4_t cmp = compare_gtge_signed(bit, out, BIT4_1);
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switch (cmp) {
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case BIT4_1: // bit >= 0
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out = bit;
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break;
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case BIT4_0: // bit < 0
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out = ~bit;
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out += 1;
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break;
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default: // There's an X.
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out = vvp_vector4_t(bit.size(), BIT4_X);
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break;
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}
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vvp_send_vec4(ptr.ptr()->out, out);
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}
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void vvp_arith_abs::recv_real(vvp_net_ptr_t ptr, double bit)
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{
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double out = fabs(bit);
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vvp_send_real(ptr.ptr()->out, out);
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}
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// Division
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vvp_arith_div::vvp_arith_div(unsigned wid, bool signed_flag)
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: vvp_arith_(wid), signed_flag_(signed_flag)
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{
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}
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vvp_arith_div::~vvp_arith_div()
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{
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}
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void vvp_arith_div::wide4_(vvp_net_ptr_t ptr)
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{
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vvp_vector2_t a2 (op_a_);
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if (a2.is_NaN()) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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vvp_vector2_t b2 (op_b_);
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if (b2.is_NaN()) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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vvp_vector2_t res2 = a2 / b2;
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vvp_send_vec4(ptr.ptr()->out, vector2_to_vector4(res2, wid_));
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}
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void vvp_arith_div::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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dispatch_operand_(ptr, bit);
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if (wid_ > 8 * sizeof(unsigned long)) {
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wide4_(ptr);
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return ;
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}
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unsigned long a;
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if (! vector4_to_value(op_a_, a)) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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unsigned long b;
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if (! vector4_to_value(op_b_, b)) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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bool negate = false;
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/* If we are doing signed divide, then take the sign out of
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the operands for now, and remember to put the sign back
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later. */
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if (signed_flag_) {
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if (op_a_.value(op_a_.size()-1)) {
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a = (-a) & ~ (-1UL << op_a_.size());
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negate = !negate;
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}
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if (op_b_.value(op_b_.size()-1)) {
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b = (-b) & ~ (-1UL << op_b_.size());
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negate = ! negate;
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}
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}
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unsigned long val = a / b;
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if (negate)
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val = -val;
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assert(wid_ <= 8*sizeof(val));
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vvp_vector4_t vval (wid_);
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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if (val & 1)
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vval.set_bit(idx, BIT4_1);
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else
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vval.set_bit(idx, BIT4_0);
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val >>= 1;
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}
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vvp_send_vec4(ptr.ptr()->out, vval);
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}
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vvp_arith_mod::vvp_arith_mod(unsigned wid, bool sf)
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: vvp_arith_(wid), signed_flag_(sf)
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{
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}
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vvp_arith_mod::~vvp_arith_mod()
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{
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}
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void vvp_arith_mod::wide_(vvp_net_ptr_t ptr)
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{
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vvp_vector2_t a2 (op_a_);
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if (a2.is_NaN()) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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vvp_vector2_t b2 (op_b_);
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if (b2.is_NaN()) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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vvp_vector2_t res = a2 % b2;
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vvp_send_vec4(ptr.ptr()->out, vector2_to_vector4(res, res.size()));
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}
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void vvp_arith_mod::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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dispatch_operand_(ptr, bit);
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if (wid_ > 8 * sizeof(unsigned long)) {
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wide_(ptr);
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return ;
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}
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unsigned long a;
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if (! vector4_to_value(op_a_, a)) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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unsigned long b;
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if (! vector4_to_value(op_b_, b)) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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bool negate = false;
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/* If we are doing signed divide, then take the sign out of
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the operands for now, and remember to put the sign back
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later. */
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if (signed_flag_) {
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if (op_a_.value(op_a_.size()-1)) {
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a = (-a) & ~ (-1UL << op_a_.size());
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negate = !negate;
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}
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if (op_b_.value(op_b_.size()-1)) {
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b = (-b) & ~ (-1UL << op_b_.size());
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negate = ! negate;
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}
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}
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if (b == 0) {
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vvp_vector4_t xval (wid_);
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1)
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xval.set_bit(idx, BIT4_X);
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vvp_send_vec4(ptr.ptr()->out, xval);
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return;
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}
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unsigned long val = a % b;
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if (negate)
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val = -val;
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assert(wid_ <= 8*sizeof(val));
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vvp_vector4_t vval (wid_);
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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if (val & 1)
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vval.set_bit(idx, BIT4_1);
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else
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vval.set_bit(idx, BIT4_0);
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val >>= 1;
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}
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vvp_send_vec4(ptr.ptr()->out, vval);
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}
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// Multiplication
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vvp_arith_mult::vvp_arith_mult(unsigned wid)
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: vvp_arith_(wid)
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{
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}
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vvp_arith_mult::~vvp_arith_mult()
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{
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}
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void vvp_arith_mult::wide_(vvp_net_ptr_t ptr)
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{
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vvp_vector2_t a2 (op_a_);
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vvp_vector2_t b2 (op_b_);
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if (a2.is_NaN() || b2.is_NaN()) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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vvp_vector2_t result = a2 * b2;
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vvp_vector4_t res4 = vector2_to_vector4(result, wid_);
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vvp_send_vec4(ptr.ptr()->out, res4);
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}
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void vvp_arith_mult::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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dispatch_operand_(ptr, bit);
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if (wid_ > 8 * sizeof(unsigned long)) {
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wide_(ptr);
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return ;
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}
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unsigned long a;
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if (! vector4_to_value(op_a_, a)) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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unsigned long b;
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if (! vector4_to_value(op_b_, b)) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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unsigned long val = a * b;
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assert(wid_ <= 8*sizeof(val));
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vvp_vector4_t vval (wid_);
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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if (val & 1)
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vval.set_bit(idx, BIT4_1);
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else
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vval.set_bit(idx, BIT4_0);
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val >>= 1;
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}
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vvp_send_vec4(ptr.ptr()->out, vval);
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}
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#if 0
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void vvp_arith_mult::set(vvp_ipoint_t i, bool push, unsigned val, unsigned)
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{
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put(i, val);
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vvp_ipoint_t base = ipoint_make(i,0);
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if(wid_ > 8*sizeof(unsigned long)) {
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wide(base, push);
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return;
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}
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unsigned long a = 0, b = 0;
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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vvp_ipoint_t ptr = ipoint_index(base,idx);
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functor_t obj = functor_index(ptr);
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unsigned val = obj->ival;
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if (val & 0xaa) {
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output_x_(base, push);
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return;
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}
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if (val & 0x01)
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a += 1UL << idx;
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if (val & 0x04)
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b += 1UL << idx;
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}
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output_val_(base, push, a*b);
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}
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#endif
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#if 0
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void vvp_arith_mult::wide(vvp_ipoint_t base, bool push)
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{
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unsigned char *a, *b, *sum;
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a = new unsigned char[wid_];
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b = new unsigned char[wid_];
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sum = new unsigned char[wid_];
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unsigned mxa = 0;
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unsigned mxb = 0;
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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vvp_ipoint_t ptr = ipoint_index(base, idx);
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functor_t obj = functor_index(ptr);
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unsigned ival = obj->ival;
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if (ival & 0xaa) {
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output_x_(base, push);
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delete[]sum;
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delete[]b;
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delete[]a;
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return;
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}
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if((a[idx] = ((ival & 0x01) != 0))) mxa=idx+1;
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if((b[idx] = ((ival & 0x04) != 0))) mxb=idx;
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sum[idx] = 0;
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}
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/* do the a*b multiply using the long method we learned in
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grade school. We know at this point that there are no X or
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Z values in the a or b vectors. */
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for(unsigned i=0 ; i<=mxb ; i += 1) {
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if(b[i]) {
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unsigned char carry=0;
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unsigned char temp;
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for(unsigned j=0 ; j<=mxa ; j += 1) {
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if((i+j) >= wid_)
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break;
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temp=sum[i+j] + a[j] + carry;
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sum[i+j]=(temp&1);
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carry=(temp>>1);
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}
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}
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}
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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vvp_ipoint_t ptr = ipoint_index(base,idx);
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functor_t obj = functor_index(ptr);
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unsigned val = sum[idx];
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obj->put_oval(val, push);
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}
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delete[]sum;
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delete[]b;
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delete[]a;
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}
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#endif
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// Power
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vvp_arith_pow::vvp_arith_pow(unsigned wid, bool signed_flag)
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: vvp_arith_(wid), signed_flag_(signed_flag)
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{
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}
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vvp_arith_pow::~vvp_arith_pow()
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{
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}
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void vvp_arith_pow::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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dispatch_operand_(ptr, bit);
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vvp_vector4_t res4;
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if (signed_flag_) {
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if (op_a_.has_xz() || op_b_.has_xz()) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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double ad, bd;
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vector4_to_value(op_a_, ad, true);
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vector4_to_value(op_b_, bd, true);
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res4 = double_to_vector4(pow(ad, bd), wid_);
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} else {
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vvp_vector2_t a2 (op_a_);
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vvp_vector2_t b2 (op_b_);
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if (a2.is_NaN() || b2.is_NaN()) {
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vvp_send_vec4(ptr.ptr()->out, x_val_);
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return;
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}
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vvp_vector2_t result = pow(a2, b2);
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res4 = vector2_to_vector4(result, wid_);
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}
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vvp_send_vec4(ptr.ptr()->out, res4);
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}
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// Addition
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vvp_arith_sum::vvp_arith_sum(unsigned wid)
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: vvp_arith_(wid)
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{
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}
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vvp_arith_sum::~vvp_arith_sum()
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{
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}
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void vvp_arith_sum::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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dispatch_operand_(ptr, bit);
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vvp_net_t*net = ptr.ptr();
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vvp_vector4_t value (wid_);
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/* Pad input vectors with this value to widen to the desired
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output width. */
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const vvp_bit4_t pad = BIT4_0;
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vvp_bit4_t carry = BIT4_0;
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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vvp_bit4_t a = (idx >= op_a_.size())? pad : op_a_.value(idx);
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vvp_bit4_t b = (idx >= op_b_.size())? pad : op_b_.value(idx);
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vvp_bit4_t cur = add_with_carry(a, b, carry);
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if (cur == BIT4_X) {
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vvp_send_vec4(net->out, x_val_);
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return;
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}
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value.set_bit(idx, cur);
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}
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vvp_send_vec4(net->out, value);
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}
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vvp_arith_sub::vvp_arith_sub(unsigned wid)
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: vvp_arith_(wid)
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{
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}
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vvp_arith_sub::~vvp_arith_sub()
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{
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}
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/*
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* Subtraction works by adding the 2s complement of the B input from
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* the A input. The 2s complement is the 1s complement plus one, so we
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* further reduce the operation to adding in the inverted value and
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* adding a correction.
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*/
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void vvp_arith_sub::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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dispatch_operand_(ptr, bit);
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vvp_net_t*net = ptr.ptr();
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vvp_vector4_t value (wid_);
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/* Pad input vectors with this value to widen to the desired
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output width. */
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const vvp_bit4_t pad = BIT4_1;
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vvp_bit4_t carry = BIT4_1;
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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vvp_bit4_t a = (idx >= op_a_.size())? pad : op_a_.value(idx);
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vvp_bit4_t b = (idx >= op_b_.size())? pad : ~op_b_.value(idx);
|
|
vvp_bit4_t cur = add_with_carry(a, b, carry);
|
|
|
|
if (cur == BIT4_X) {
|
|
vvp_send_vec4(net->out, x_val_);
|
|
return;
|
|
}
|
|
|
|
value.set_bit(idx, cur);
|
|
}
|
|
|
|
vvp_send_vec4(net->out, value);
|
|
}
|
|
|
|
vvp_cmp_eeq::vvp_cmp_eeq(unsigned wid)
|
|
: vvp_arith_(wid)
|
|
{
|
|
}
|
|
|
|
void vvp_cmp_eeq::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_vector4_t eeq (1);
|
|
eeq.set_bit(0, BIT4_1);
|
|
|
|
assert(op_a_.size() == op_b_.size());
|
|
for (unsigned idx = 0 ; idx < op_a_.size() ; idx += 1)
|
|
if (op_a_.value(idx) != op_b_.value(idx)) {
|
|
eeq.set_bit(0, BIT4_0);
|
|
break;
|
|
}
|
|
|
|
|
|
vvp_net_t*net = ptr.ptr();
|
|
vvp_send_vec4(net->out, eeq);
|
|
}
|
|
|
|
vvp_cmp_nee::vvp_cmp_nee(unsigned wid)
|
|
: vvp_arith_(wid)
|
|
{
|
|
}
|
|
|
|
void vvp_cmp_nee::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_vector4_t eeq (1);
|
|
eeq.set_bit(0, BIT4_0);
|
|
|
|
assert(op_a_.size() == op_b_.size());
|
|
for (unsigned idx = 0 ; idx < op_a_.size() ; idx += 1)
|
|
if (op_a_.value(idx) != op_b_.value(idx)) {
|
|
eeq.set_bit(0, BIT4_1);
|
|
break;
|
|
}
|
|
|
|
|
|
vvp_net_t*net = ptr.ptr();
|
|
vvp_send_vec4(net->out, eeq);
|
|
}
|
|
|
|
vvp_cmp_eq::vvp_cmp_eq(unsigned wid)
|
|
: vvp_arith_(wid)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Compare Vector a and Vector b. If in any bit position the a and b
|
|
* bits are known and different, then the result is 0. Otherwise, if
|
|
* there are X/Z bits anywhere in A or B, the result is X. Finally,
|
|
* the result is 1.
|
|
*/
|
|
void vvp_cmp_eq::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
if (op_a_.size() != op_b_.size()) {
|
|
cerr << "COMPARISON size mismatch. "
|
|
<< "a=" << op_a_ << ", b=" << op_b_ << endl;
|
|
assert(0);
|
|
}
|
|
|
|
vvp_vector4_t res (1);
|
|
res.set_bit(0, BIT4_1);
|
|
|
|
for (unsigned idx = 0 ; idx < op_a_.size() ; idx += 1) {
|
|
vvp_bit4_t a = op_a_.value(idx);
|
|
vvp_bit4_t b = op_b_.value(idx);
|
|
|
|
if (a == BIT4_X)
|
|
res.set_bit(0, BIT4_X);
|
|
else if (a == BIT4_Z)
|
|
res.set_bit(0, BIT4_X);
|
|
else if (b == BIT4_X)
|
|
res.set_bit(0, BIT4_X);
|
|
else if (b == BIT4_Z)
|
|
res.set_bit(0, BIT4_X);
|
|
else if (a != b) {
|
|
res.set_bit(0, BIT4_0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
vvp_net_t*net = ptr.ptr();
|
|
vvp_send_vec4(net->out, res);
|
|
}
|
|
|
|
|
|
vvp_cmp_ne::vvp_cmp_ne(unsigned wid)
|
|
: vvp_arith_(wid)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Compare Vector a and Vector b. If in any bit position the a and b
|
|
* bits are known and different, then the result is 1. Otherwise, if
|
|
* there are X/Z bits anywhere in A or B, the result is X. Finally,
|
|
* the result is 0.
|
|
*/
|
|
void vvp_cmp_ne::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
assert(op_a_.size() == op_b_.size());
|
|
|
|
vvp_vector4_t res (1);
|
|
res.set_bit(0, BIT4_0);
|
|
|
|
for (unsigned idx = 0 ; idx < op_a_.size() ; idx += 1) {
|
|
vvp_bit4_t a = op_a_.value(idx);
|
|
vvp_bit4_t b = op_b_.value(idx);
|
|
|
|
if (a == BIT4_X)
|
|
res.set_bit(0, BIT4_X);
|
|
else if (a == BIT4_Z)
|
|
res.set_bit(0, BIT4_X);
|
|
else if (b == BIT4_X)
|
|
res.set_bit(0, BIT4_X);
|
|
else if (b == BIT4_Z)
|
|
res.set_bit(0, BIT4_X);
|
|
else if (a != b) {
|
|
res.set_bit(0, BIT4_1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
vvp_net_t*net = ptr.ptr();
|
|
vvp_send_vec4(net->out, res);
|
|
}
|
|
|
|
|
|
vvp_cmp_gtge_base_::vvp_cmp_gtge_base_(unsigned wid, bool flag)
|
|
: vvp_arith_(wid), signed_flag_(flag)
|
|
{
|
|
}
|
|
|
|
|
|
void vvp_cmp_gtge_base_::recv_vec4_base_(vvp_net_ptr_t ptr,
|
|
vvp_vector4_t bit,
|
|
vvp_bit4_t out_if_equal)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_bit4_t out = signed_flag_
|
|
? compare_gtge_signed(op_a_, op_b_, out_if_equal)
|
|
: compare_gtge(op_a_, op_b_, out_if_equal);
|
|
vvp_vector4_t val (1);
|
|
val.set_bit(0, out);
|
|
vvp_send_vec4(ptr.ptr()->out, val);
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
vvp_cmp_ge::vvp_cmp_ge(unsigned wid, bool flag)
|
|
: vvp_cmp_gtge_base_(wid, flag)
|
|
{
|
|
}
|
|
|
|
void vvp_cmp_ge::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
|
|
{
|
|
recv_vec4_base_(ptr, bit, BIT4_1);
|
|
}
|
|
|
|
vvp_cmp_gt::vvp_cmp_gt(unsigned wid, bool flag)
|
|
: vvp_cmp_gtge_base_(wid, flag)
|
|
{
|
|
}
|
|
|
|
void vvp_cmp_gt::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
|
|
{
|
|
recv_vec4_base_(ptr, bit, BIT4_0);
|
|
}
|
|
|
|
|
|
vvp_shiftl::vvp_shiftl(unsigned wid)
|
|
: vvp_arith_(wid)
|
|
{
|
|
}
|
|
|
|
vvp_shiftl::~vvp_shiftl()
|
|
{
|
|
}
|
|
|
|
void vvp_shiftl::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_vector4_t out (op_a_.size());
|
|
|
|
unsigned long shift;
|
|
if (! vector4_to_value(op_b_, shift)) {
|
|
vvp_send_vec4(ptr.ptr()->out, x_val_);
|
|
return;
|
|
}
|
|
|
|
if (shift > out.size())
|
|
shift = out.size();
|
|
|
|
for (unsigned idx = 0 ; idx < shift ; idx += 1)
|
|
out.set_bit(idx, BIT4_0);
|
|
|
|
for (unsigned idx = shift ; idx < out.size() ; idx += 1)
|
|
out.set_bit(idx, op_a_.value(idx-shift));
|
|
|
|
vvp_send_vec4(ptr.ptr()->out, out);
|
|
}
|
|
|
|
vvp_shiftr::vvp_shiftr(unsigned wid, bool signed_flag)
|
|
: vvp_arith_(wid), signed_flag_(signed_flag)
|
|
{
|
|
}
|
|
|
|
vvp_shiftr::~vvp_shiftr()
|
|
{
|
|
}
|
|
|
|
void vvp_shiftr::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_vector4_t out (op_a_.size());
|
|
|
|
unsigned long shift;
|
|
if (! vector4_to_value(op_b_, shift)) {
|
|
vvp_send_vec4(ptr.ptr()->out, x_val_);
|
|
return;
|
|
}
|
|
|
|
if (shift > out.size())
|
|
shift = out.size();
|
|
|
|
for (unsigned idx = shift ; idx < out.size() ; idx += 1)
|
|
out.set_bit(idx-shift, op_a_.value(idx));
|
|
|
|
vvp_bit4_t pad = BIT4_0;
|
|
if (signed_flag_ && op_a_.size() > 0)
|
|
pad = op_a_.value(op_a_.size()-1);
|
|
|
|
for (unsigned idx = 0 ; idx < shift ; idx += 1)
|
|
out.set_bit(idx+out.size()-shift, pad);
|
|
|
|
vvp_send_vec4(ptr.ptr()->out, out);
|
|
}
|
|
|
|
|
|
vvp_arith_real_::vvp_arith_real_()
|
|
{
|
|
op_a_ = 0.0;
|
|
op_b_ = 0.0;
|
|
}
|
|
|
|
void vvp_arith_real_::dispatch_operand_(vvp_net_ptr_t ptr, double bit)
|
|
{
|
|
switch (ptr.port()) {
|
|
case 0:
|
|
op_a_ = bit;
|
|
break;
|
|
case 1:
|
|
op_b_ = bit;
|
|
break;
|
|
default:
|
|
fprintf(stderr, "Unsupported port type %d.\n", ptr.port());
|
|
assert(0);
|
|
}
|
|
}
|
|
|
|
|
|
/* Real multiplication. */
|
|
vvp_arith_mult_real::vvp_arith_mult_real()
|
|
{
|
|
}
|
|
|
|
vvp_arith_mult_real::~vvp_arith_mult_real()
|
|
{
|
|
}
|
|
|
|
void vvp_arith_mult_real::recv_real(vvp_net_ptr_t ptr, double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
double val = op_a_ * op_b_;
|
|
vvp_send_real(ptr.ptr()->out, val);
|
|
}
|
|
|
|
/* Real power. */
|
|
vvp_arith_pow_real::vvp_arith_pow_real()
|
|
{
|
|
}
|
|
|
|
vvp_arith_pow_real::~vvp_arith_pow_real()
|
|
{
|
|
}
|
|
|
|
void vvp_arith_pow_real::recv_real(vvp_net_ptr_t ptr, double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
double val = pow(op_a_, op_b_);
|
|
vvp_send_real(ptr.ptr()->out, val);
|
|
}
|
|
|
|
/* Real division. */
|
|
vvp_arith_div_real::vvp_arith_div_real()
|
|
{
|
|
}
|
|
|
|
vvp_arith_div_real::~vvp_arith_div_real()
|
|
{
|
|
}
|
|
|
|
void vvp_arith_div_real::recv_real(vvp_net_ptr_t ptr, double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
double val = op_a_ / op_b_;
|
|
vvp_send_real(ptr.ptr()->out, val);
|
|
}
|
|
|
|
/* Real modulus. */
|
|
vvp_arith_mod_real::vvp_arith_mod_real()
|
|
{
|
|
}
|
|
|
|
vvp_arith_mod_real::~vvp_arith_mod_real()
|
|
{
|
|
}
|
|
|
|
void vvp_arith_mod_real::recv_real(vvp_net_ptr_t ptr, double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
double val = fmod(op_a_, op_b_);
|
|
vvp_send_real(ptr.ptr()->out, val);
|
|
}
|
|
|
|
/* Real summation. */
|
|
vvp_arith_sum_real::vvp_arith_sum_real()
|
|
{
|
|
}
|
|
|
|
vvp_arith_sum_real::~vvp_arith_sum_real()
|
|
{
|
|
}
|
|
|
|
void vvp_arith_sum_real::recv_real(vvp_net_ptr_t ptr, double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
double val = op_a_ + op_b_;
|
|
vvp_send_real(ptr.ptr()->out, val);
|
|
}
|
|
|
|
/* Real subtraction. */
|
|
vvp_arith_sub_real::vvp_arith_sub_real()
|
|
{
|
|
}
|
|
|
|
vvp_arith_sub_real::~vvp_arith_sub_real()
|
|
{
|
|
}
|
|
|
|
void vvp_arith_sub_real::recv_real(vvp_net_ptr_t ptr, double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
double val = op_a_ - op_b_;
|
|
vvp_send_real(ptr.ptr()->out, val);
|
|
}
|
|
|
|
/* Real compare equal. */
|
|
vvp_cmp_eq_real::vvp_cmp_eq_real()
|
|
{
|
|
}
|
|
|
|
void vvp_cmp_eq_real::recv_real(vvp_net_ptr_t ptr, const double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_vector4_t res (1);
|
|
if (op_a_ == op_b_) res.set_bit(0, BIT4_1);
|
|
else res.set_bit(0, BIT4_0);
|
|
|
|
vvp_send_vec4(ptr.ptr()->out, res);
|
|
}
|
|
|
|
/* Real compare not equal. */
|
|
vvp_cmp_ne_real::vvp_cmp_ne_real()
|
|
{
|
|
}
|
|
|
|
void vvp_cmp_ne_real::recv_real(vvp_net_ptr_t ptr, const double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_vector4_t res (1);
|
|
if (op_a_ != op_b_) res.set_bit(0, BIT4_1);
|
|
else res.set_bit(0, BIT4_0);
|
|
|
|
vvp_send_vec4(ptr.ptr()->out, res);
|
|
}
|
|
|
|
/* Real compare greater than or equal. */
|
|
vvp_cmp_ge_real::vvp_cmp_ge_real()
|
|
{
|
|
}
|
|
|
|
void vvp_cmp_ge_real::recv_real(vvp_net_ptr_t ptr, const double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_vector4_t res (1);
|
|
if (op_a_ >= op_b_) res.set_bit(0, BIT4_1);
|
|
else res.set_bit(0, BIT4_0);
|
|
|
|
vvp_send_vec4(ptr.ptr()->out, res);
|
|
}
|
|
|
|
/* Real compare greater than. */
|
|
vvp_cmp_gt_real::vvp_cmp_gt_real()
|
|
{
|
|
}
|
|
|
|
void vvp_cmp_gt_real::recv_real(vvp_net_ptr_t ptr, const double bit)
|
|
{
|
|
dispatch_operand_(ptr, bit);
|
|
|
|
vvp_vector4_t res (1);
|
|
if (op_a_ > op_b_) res.set_bit(0, BIT4_1);
|
|
else res.set_bit(0, BIT4_0);
|
|
|
|
vvp_send_vec4(ptr.ptr()->out, res);
|
|
}
|