53 lines
1.1 KiB
Verilog
53 lines
1.1 KiB
Verilog
// A few simple tests of translating parameters to generics
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module top();
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wire [7:0] v1, v2, v3;
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wire [7:0] w1, w2, w3;
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child c1(v1, w1);
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child c2(v2, w2);
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child c3(v3, w3);
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defparam c1.MY_VALUE = 6;
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defparam c2.MY_VALUE = 44;
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initial begin
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#2;
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$display("c1 reg value: %d", v1);
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$display("c2 reg value: %d", v2);
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$display("c3 reg value: %d", v3);
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$display("c1 wire value: %d", w1);
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$display("c2 wire value: %d", w2);
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$display("c3 wire value: %d", w3);
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if (v1 !== 6)
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$display("FAILED - v1 !== 6");
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else if (v2 !== 44)
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$display("FAILED - v2 !== 44");
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else if (v3 !== 12)
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$display("FAILED - v3 !== 12");
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else if (w1 !== 7)
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$display("FAILED - v1 !== 7");
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else if (w2 !== 45)
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$display("FAILED - v2 !== 45");
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else if (w3 !== 13)
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$display("FAILED - v3 !== 13");
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else
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$display("PASSED");
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end
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endmodule // top
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module child(value, value_w);
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output [7:0] value, value_w;
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reg [7:0] value;
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parameter MY_VALUE = 12;
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assign value_w = MY_VALUE + 1;
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// Make a non-trivial process
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initial begin
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#1;
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value <= MY_VALUE;
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end
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endmodule // child
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