39 lines
623 B
Verilog
39 lines
623 B
Verilog
module testbench();
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reg [3:0] a, b;
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initial begin
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a = 1;
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b = 2;
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#1;
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a = a + b;
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b = a + b;
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if (a !== 3)
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begin
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$display("FAILED -- a !== 3");
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$finish;
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end
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if (b !== 5)
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begin
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$display("FAILED -- b !== 5");
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$finish;
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end
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#2;
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$display("PASSED");
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end // initial begin
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initial begin
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#2;
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if (a !== 3)
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begin
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$display("FAILED -- a (signal) !== 3");
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$finish;
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end
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if (b !== 5)
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begin
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$display("FAILED -- b (signal) !== 5");
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$finish;
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end
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end
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endmodule // testbench
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