103 lines
2.8 KiB
C++
103 lines
2.8 KiB
C++
#ifndef IVL_dff_H
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#define IVL_dff_H
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/*
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* Copyright (c) 2005-2016 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "vvp_net.h"
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/*
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* The vvp_dff implements an arbitrary width D-type FF. The clock,
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* clock-enable, and asynchronous set/clear inputs are single bits.
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* Both positive and negative edge triggered flip-flops are supported.
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* An output is propagated on the chosen edge of the clock input, or
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* on the rising edge of the asynchronous set/clear input. Ports are:
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*
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* port-0: D input
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* port-1: Clock input
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* port-2: Clock Enable input
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* port-3: Asynchronous Set/Clear input.
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*
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* The base vvp_dff does not implement an asynchronous set/clear.
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*/
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class vvp_dff : public vvp_net_fun_t {
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public:
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explicit vvp_dff(unsigned width, bool negedge);
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~vvp_dff();
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void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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vvp_context_t);
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void recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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unsigned base, unsigned wid, unsigned vwid,
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vvp_context_t ctx);
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private:
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virtual void recv_async(vvp_net_ptr_t port);
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vvp_bit4_t clk_active_ : 8;
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vvp_bit4_t clk_ : 8;
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vvp_bit4_t ena_ : 8;
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vvp_bit4_t asc_ : 8;
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protected:
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vvp_vector4_t d_;
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};
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/*
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* This variant implements an asynchronous clear to all zeros.
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*/
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class vvp_dff_aclr : public vvp_dff {
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public:
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explicit vvp_dff_aclr(unsigned width, bool negedge);
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private:
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void recv_async(vvp_net_ptr_t port);
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};
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/*
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* This variant implements an asynchronous set to all ones.
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*/
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class vvp_dff_aset : public vvp_dff {
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public:
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explicit vvp_dff_aset(unsigned width, bool negedge);
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private:
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void recv_async(vvp_net_ptr_t port);
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};
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/*
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* This variant implements an asynchronous set to a specified constant
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* vector value.
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*/
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class vvp_dff_asc : public vvp_dff {
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public:
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explicit vvp_dff_asc(unsigned width, bool negedge, char*asc_value);
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private:
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void recv_async(vvp_net_ptr_t port);
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vvp_vector4_t asc_value_;
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};
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#endif /* IVL_dff_H */
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