362 lines
11 KiB
C++
362 lines
11 KiB
C++
/*
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* Copyright (c) 1998-2010 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "config.h"
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# include <iostream>
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# include "functor.h"
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# include "netlist.h"
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# include "netmisc.h"
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class xnfio_f : public functor_t {
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public:
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void signal(Design*des, NetNet*sig);
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void lpm_compare(Design*des, NetCompare*dev);
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private:
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bool compare_sideb_const(Design*des, NetCompare*dev);
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};
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static bool is_a_pad(const NetNet*net)
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{
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if (net->attribute(perm_string::literal("PAD")) == verinum())
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return false;
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return true;
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}
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/*
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* The xnfio function looks for the PAD signals in the design, and
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* generates the needed IOB devices to handle being connected to the
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* actual FPGA PAD. This will add items to the netlist if needed.
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*
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* FIXME: If there is a DFF connected to the pad, try to convert it
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* to an IO DFF instead. This would save a CLB, and it is
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* really lame to not do the obvious optimization.
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*/
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static NetLogic* make_obuf(Design*des, NetNet*net)
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{
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NetScope* scope = net->scope();
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assert(scope);
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assert(net->pin_count() == 1);
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/* FIXME: If there is nothing internally driving this PAD, I
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can connect the PAD to a pullup and disconnect it from the
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rest of the circuit. This would save routing resources. */
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if (count_outputs(net->pin(0)) <= 0) {
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cerr << net->get_line() << ":warning: No outputs to OPAD: "
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<< net->name() << endl;
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return 0;
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}
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assert(count_outputs(net->pin(0)) > 0);
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/* Look for an existing OBUF connected to this signal. If it
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is there, then no need to add one. */
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Nexus*nex = net->pin(0).nexus();
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for (Link*idx = nex->first_nlink()
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; idx ; idx = idx->next_nlink()) {
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NetLogic*tmp;
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if ((tmp = dynamic_cast<NetLogic*>(idx->get_obj())) == 0)
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continue;
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// Try to use an existing BUF as an OBUF. This moves the
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// BUF into the IOB.
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if ((tmp->type() == NetLogic::BUF)
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&& (count_inputs(tmp->pin(0)) == 0)
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&& (count_outputs(tmp->pin(0)) == 1)
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&& (idx->get_pin() == 0) ) {
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tmp->attribute(perm_string::literal("XNF-LCA"),
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verinum("OBUF:O,I"));
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return tmp;
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}
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// Try to use an existing INV as an OBUF. Certain
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// technologies support inverting the input of an OBUF,
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// which looks just like an inverter. This uses the
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// available resources of an IOB to optimize away an
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// otherwise expensive inverter.
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if ((tmp->type() == NetLogic::NOT)
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&& (count_inputs(tmp->pin(0)) == 0)
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&& (count_outputs(tmp->pin(0)) == 1)
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&& (idx->get_pin() == 0) ) {
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tmp->attribute(perm_string::literal("XNF-LCA"),
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verinum("OBUF:O,~I"));
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return tmp;
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}
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// Try to use an existing bufif1 as an OBUFT. Of course
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// this will only work if the output of the bufif1 is
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// connected only to the pad. Handle bufif0 the same
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// way, but the T input is inverted.
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if ((tmp->type() == NetLogic::BUFIF1)
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&& (count_inputs(tmp->pin(0)) == 0)
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&& (count_outputs(tmp->pin(0)) == 1)
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&& (idx->get_pin() == 0) ) {
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tmp->attribute(perm_string::literal("XNF-LCA"),
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verinum("OBUFT:O,I,~T"));
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return tmp;
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}
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if ((tmp->type() == NetLogic::BUFIF0)
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&& (count_inputs(tmp->pin(0)) == 0)
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&& (count_outputs(tmp->pin(0)) == 1)
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&& (idx->get_pin() == 0) ) {
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tmp->attribute(perm_string::literal("XNF-LCA"),
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verinum("OBUFT:O,I,T"));
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return tmp;
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}
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}
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// Can't seem to find a way to rearrange the existing netlist,
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// so I am stuck creating a new buffer, the OBUF.
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NetLogic*buf = new NetLogic(scope, scope->local_symbol(),
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2, NetLogic::BUF);
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des->add_node(buf);
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buf->attribute(perm_string::literal("XNF-LCA"), verinum("OBUF:O,I"));
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// Put the buffer between this signal and the rest of the
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// netlist.
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connect(net->pin(0), buf->pin(1));
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net->pin(0).unlink();
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connect(net->pin(0), buf->pin(0));
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// It is possible, in putting an OBUF between net and the rest
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// of the netlist, to create a ring without a signal. Detect
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// this case and create a new signal.
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if (count_signals(buf->pin(1)) == 0) {
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NetNet*tmp = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE);
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tmp->local_flag(true);
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connect(buf->pin(1), tmp->pin(0));
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}
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return buf;
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}
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static void absorb_OFF(Design*des, NetLogic*buf)
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{
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/* If the nexus connects is not a simple point-to-point link,
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then I can't drag it into the IOB. Give up. */
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if (count_outputs(buf->pin(1)) != 1)
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return;
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if (count_inputs(buf->pin(1)) != 1)
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return;
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/* For now, only support OUTFF. */
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if (buf->type() != NetLogic::BUF)
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return;
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Link*drv = find_next_output(&buf->pin(1));
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assert(drv);
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/* Make sure the device is a FF with width 1. */
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NetFF*ff = dynamic_cast<NetFF*>(drv->get_obj());
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if (ff == 0)
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return;
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if (ff->width() != 1)
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return;
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if (ff->attribute(perm_string::literal("LPM_FFType")) != verinum("DFF"))
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return;
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/* Connect the flip-flop output to the buffer output and
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delete the buffer. The XNF OUTFF can buffer the pin. */
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connect(ff->pin_Q(0), buf->pin(0));
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delete buf;
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/* Finally, build up an XNF-LCA value that defines this
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devices as an OUTFF and gives each pin an XNF name. */
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const char**names = new const char*[ff->pin_count()];
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for (unsigned idx = 0 ; idx < ff->pin_count() ; idx += 1)
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names[idx] = "";
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if (ff->attribute(perm_string::literal("Clock:LPM_Polarity")) == verinum("INVERT"))
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names[ff->pin_Clock().get_pin()] = "~C";
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else
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names[ff->pin_Clock().get_pin()] = "C";
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names[ff->pin_Data(0).get_pin()] = "D";
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names[ff->pin_Q(0).get_pin()] = "Q";
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string lname = string("OUTFF:") + names[0];
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for (unsigned idx = 1 ; idx < ff->pin_count() ; idx += 1)
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lname = lname + "," + names[idx];
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delete[]names;
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ff->attribute(perm_string::literal("XNF-LCA"), lname);
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}
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static void make_ibuf(Design*des, NetNet*net)
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{
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NetScope*scope = net->scope();
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assert(scope);
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assert(net->pin_count() == 1);
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// XXXX For now, require at least one input.
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assert(count_inputs(net->pin(0)) > 0);
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/* Look for an existing BUF connected to this signal and
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suitably connected that I can use it as an IBUF. */
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Nexus*nex = net->pin(0).nexus();
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for (Link*idx = nex->first_nlink()
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; idx ; idx = idx->next_nlink()) {
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NetLogic*tmp;
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if ((tmp = dynamic_cast<NetLogic*>(idx->get_obj())) == 0)
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continue;
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if (tmp->attribute(perm_string::literal("XNF-LCA")) != verinum())
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continue;
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// Found a BUF, it is only usable if the only input is
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// the signal and there are no other inputs.
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if ((tmp->type() == NetLogic::BUF) &&
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(count_inputs(tmp->pin(1)) == 1) &&
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(count_outputs(tmp->pin(1)) == 0)) {
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tmp->attribute(perm_string::literal("XNF-LCA"), verinum("IBUF:O,I"));
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return;
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}
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}
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// I give up, create an IBUF.
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NetLogic*buf = new NetLogic(scope, scope->local_symbol(),
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2, NetLogic::BUF);
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des->add_node(buf);
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buf->attribute(perm_string::literal("XNF-LCA"), verinum("IBUF:O,I"));
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// Put the buffer between this signal and the rest of the
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// netlist.
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connect(net->pin(0), buf->pin(0));
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net->pin(0).unlink();
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connect(net->pin(0), buf->pin(1));
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// It is possible, in putting an OBUF between net and the rest
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// of the netlist, to create a ring without a signal. Detect
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// this case and create a new signal.
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if (count_signals(buf->pin(0)) == 0) {
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NetNet*tmp = new NetNet(scope,
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scope->local_symbol(),
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NetNet::WIRE);
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connect(buf->pin(0), tmp->pin(0));
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}
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}
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void xnfio_f::signal(Design*des, NetNet*net)
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{
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if (! is_a_pad(net))
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return;
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assert(net->pin_count() == 1);
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string pattr = net->attribute(perm_string::literal("PAD")).as_string();
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switch (pattr[0]) {
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case 'i':
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case 'I':
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make_ibuf(des, net);
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break;
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case 'o':
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case 'O': {
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NetLogic*buf = make_obuf(des, net);
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if (buf == 0) break;
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absorb_OFF(des, buf);
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break;
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}
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// FIXME: Only IPAD and OPAD supported. Need to
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// add support for IOPAD.
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default:
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assert(0);
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break;
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}
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}
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/*
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* Attempt some XNF specific optimizations on comparators.
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*/
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void xnfio_f::lpm_compare(Design*des, NetCompare*dev)
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{
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if (compare_sideb_const(des, dev))
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return;
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return;
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}
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bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
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{
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/* Even if side B is all constant, if there are more than 4
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signals on side A we will not be able to fit the operation
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into a function unit, so we might as well accept a
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comparator. Give up. */
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if (dev->width() > 4)
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return false;
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NetScope*scope = dev->scope();
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verinum side (verinum::V0, dev->width());
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/* Is the B side all constant? */
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for (unsigned idx = 0 ; idx < dev->width() ; idx += 1) {
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if (! dev->pin_DataB(idx).nexus()->drivers_constant())
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return false;
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side.set(idx, dev->pin_DataB(idx).nexus()->driven_value());
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}
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/* Handle the special case of comparing A to 0. Use an N-input
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NOR gate to return 0 if any of the bits is not 0. */
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if ((side.as_ulong() == 0) && (count_inputs(dev->pin_AEB()) > 0)) {
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NetLogic*sub = new NetLogic(scope, dev->name(), dev->width()+1,
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NetLogic::NOR);
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connect(sub->pin(0), dev->pin_AEB());
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for (unsigned idx = 0 ; idx < dev->width() ; idx += 1)
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connect(sub->pin(idx+1), dev->pin_DataA(idx));
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delete dev;
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des->add_node(sub);
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return true;
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}
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/* Handle the special case of comparing A to 0. Use an N-input
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NOR gate to return 0 if any of the bits is not 0. */
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if ((side.as_ulong() == 0) && (count_inputs(dev->pin_ANEB()) > 0)) {
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NetLogic*sub = new NetLogic(scope, dev->name(), dev->width()+1,
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NetLogic::OR);
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connect(sub->pin(0), dev->pin_ANEB());
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for (unsigned idx = 0 ; idx < dev->width() ; idx += 1)
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connect(sub->pin(idx+1), dev->pin_DataA(idx));
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delete dev;
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des->add_node(sub);
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return true;
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}
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return false;
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}
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void xnfio(Design*des)
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{
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xnfio_f xnfio_obj;
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des->functor(&xnfio_obj);
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}
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