142 lines
4.1 KiB
C++
142 lines
4.1 KiB
C++
/*
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* VHDL code generator for Icarus Verilog.
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*
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* Copyright (C) 2008 Nick Gasson (nick@nickg.me.uk)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "version_base.h"
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#include "version_tag.h"
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#include "vhdl_target.h"
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#include "state.hh"
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#include <iostream>
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#include <fstream>
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#include <cstdarg>
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#include <cstdio>
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#include <cassert>
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#include <cstring>
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#include <cstdlib>
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static const char*version_string =
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"Icarus Verilog VHDL Code Generator " VERSION " (" VERSION_TAG ")\n\n"
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"Copyright (C) 2008 Nick Gasson (nick@nickg.me.uk)\n\n"
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" This program is free software; you can redistribute it and/or modify\n"
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" it under the terms of the GNU General Public License as published by\n"
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" the Free Software Foundation; either version 2 of the License, or\n"
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" (at your option) any later version.\n"
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"\n"
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" This program is distributed in the hope that it will be useful,\n"
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" but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
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" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"
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" GNU General Public License for more details.\n"
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"\n"
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" You should have received a copy of the GNU General Public License along\n"
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" with this program; if not, write to the Free Software Foundation, Inc.,\n"
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" 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n"
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;
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static int g_errors = 0; // Total number of errors encountered
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static ivl_design_t g_design;
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/*
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* Called when an unrecoverable problem is encountered.
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*/
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void error(const char *fmt, ...)
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{
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std::va_list args;
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va_start(args, fmt);
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std::printf("VHDL conversion error: "); // Source/line number?
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std::vprintf(fmt, args);
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std::putchar('\n');
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va_end(args);
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g_errors++;
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}
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/*
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* Print a message only if -pdebug was specified.
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*/
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void debug_msg(const char *fmt, ...)
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{
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std::va_list args;
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va_start(args, fmt);
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if (std::strcmp(ivl_design_flag(g_design, "debug"), "")) {
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std::fputs("[DEBUG] ", stdout);
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std::vprintf(fmt, args);
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std::putchar('\n');
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}
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va_end(args);
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}
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ivl_design_t get_vhdl_design()
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{
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return g_design;
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}
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extern "C" int target_design(ivl_design_t des)
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{
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ivl_scope_t *roots;
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unsigned int nroots;
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ivl_design_roots(des, &roots, &nroots);
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g_design = des;
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for (unsigned int i = 0; i < nroots; i++)
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draw_scope(roots[i], NULL);
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// Only generate processes if there were no errors generating entities
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// (otherwise the necessary information won't be present)
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if (0 == g_errors)
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ivl_design_process(des, draw_process, NULL);
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// Write the generated elements to the output file
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// only if there were no errors generating entities or processes
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if (0 == g_errors) {
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const char *ofname = ivl_design_flag(des, "-o");
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ofstream outfile(ofname);
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outfile << "-- This VHDL was converted from Verilog using the" << endl
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<< "-- Icarus Verilog VHDL Code Generator " VERSION
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" (" VERSION_TAG ")" << endl << endl;
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// If the user passed -pdepth=N then only emit entities with
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// depth < N
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// I.e. -pdepth=1 emits only the top-level entity
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// If max_depth is zero then all entities will be emitted
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// (This is handy since it means we can use atoi ;-)
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int max_depth = std::atoi(ivl_design_flag(des, "depth"));
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emit_all_entities(outfile, max_depth);
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}
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// Clean up
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free_all_vhdl_objects();
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return g_errors;
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}
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extern "C" const char* target_query(const char*key)
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{
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if (strcmp(key, "version") == 0) return version_string;
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return 0;
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}
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