361 lines
9.2 KiB
Plaintext
361 lines
9.2 KiB
Plaintext
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%{
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/*
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* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "config.h"
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# include <iostream>
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/*
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* This file implements synthesis based on matching threads and
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* converting them to equivalent devices. The trick here is that the
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* proc_match_t functor can be used to scan a process and generate a
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* string of tokens. That string of tokens can then be matched by the
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* rules to determine what kind of device is to be made.
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*/
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# include "netlist.h"
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# include "netmisc.h"
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# include "functor.h"
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# include <assert.h>
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struct syn_token_t {
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int token;
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NetAssignBase*assign;
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NetProcTop*top;
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NetEvWait*evwait;
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NetEvent*event;
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NetExpr*expr;
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syn_token_t*next_;
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};
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#define YYSTYPE syn_token_t*
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static int yylex();
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static void yyerror(const char*);
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static Design*des_;
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static void make_DFF_CE(Design*des, NetProcTop*top, NetEvWait*wclk,
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NetEvent*eclk, NetExpr*cexp, NetAssignBase*asn);
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%}
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%token S_ALWAYS S_ASSIGN S_ASSIGN_MEM S_ASSIGN_MUX S_ELSE S_EVENT
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%token S_EXPR S_IF S_INITIAL
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%%
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start
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/* These rules match simple DFF devices. Clocked assignments are
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simply implemented as DFF, and a CE is easily expressed with a
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conditional statement. The typical Verilog that get these are:
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always @(posedge CLK) Q = D
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always @(negedge CLK) Q = D
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always @(posedge CLK) if (CE) Q = D;
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always @(negedge CLK) if (CE) Q = D;
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The width of Q and D cause a wide register to be created. The
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code generators generally implement that as an array of
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flip-flops. */
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: S_ALWAYS '@' '(' S_EVENT ')' S_ASSIGN ';'
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{ make_DFF_CE(des_, $1->top, $2->evwait, $4->event,
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0, $6->assign);
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}
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| S_ALWAYS '@' '(' S_EVENT ')' S_IF S_EXPR S_ASSIGN ';' ';'
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{ make_DFF_CE(des_, $1->top, $2->evwait, $4->event,
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$7->expr, $8->assign);
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}
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/* Unconditional assignments in initial blocks should be made into
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initializers wherever possible. */
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;
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%%
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/* Various actions. */
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static void hookup_DFF_CE(NetFF*ff, NetESignal*d, NetEvProbe*pclk,
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NetNet*ce, NetAssign_*a, unsigned rval_pinoffset)
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{
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// a->sig() is a *NetNet, which doesn't have the loff_ and
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// lwid_ context. Add the correction for loff_ ourselves.
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// This extra calculation allows for assignments like:
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// lval[7:1] <= foo;
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// where lval is really a "reg [7:0]". In other words, part
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// selects in the l-value are handled by loff and the lwidth().
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connect(ff->pin_Data(), d->sig()->pin(0));
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connect(ff->pin_Q(), a->sig()->pin(0));
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connect(ff->pin_Clock(), pclk->pin(0));
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if (ce) connect(ff->pin_Enable(), ce->pin(0));
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ff->attribute(perm_string::literal("LPM_FFType"), verinum("DFF"));
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if (pclk->edge() == NetEvProbe::NEGEDGE)
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ff->attribute(perm_string::literal("Clock:LPM_Polarity"), verinum("INVERT"));
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/* This lval_ represents a reg that is a WIRE in the
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synthesized results. This function signals the destructor
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to change the REG that this l-value refers to into a
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WIRE. It is done then, at the last minute, so that pending
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synthesis can continue to work with it as a WIRE. */
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a->turn_sig_to_wire_on_release();
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}
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static void make_DFF_CE(Design*des, NetProcTop*top, NetEvWait*wclk,
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NetEvent*eclk, NetExpr*cexp, NetAssignBase*asn)
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{
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assert(asn);
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NetEvProbe*pclk = eclk->probe(0);
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NetESignal*d = dynamic_cast<NetESignal*> (asn->rval());
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NetNet*ce = cexp? cexp->synthesize(des, top->scope(), cexp) : 0;
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if (d == 0) {
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cerr << asn->get_fileline() << ": internal error: "
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<< " not a simple signal? " << *asn->rval() << endl;
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}
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assert(d);
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NetAssign_*a;
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unsigned rval_pinoffset=0;
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for (unsigned i=0; (a=asn->l_val(i)); i++) {
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// asn->l_val(i) are the set of *NetAssign_'s that form the list
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// of lval expressions. Treat each one independently, keeping
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// track of which bits of rval to use for each set of DFF inputs.
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// For example, given:
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// {carry,data} <= x + y + z;
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// run through this loop twice, where a and rval_pinoffset are
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// first data and 0, then carry and 1.
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// FIXME: ff gets its pin names wrong when loff_ is nonzero.
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if (a->sig()) {
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// cerr << "new NetFF named " << a->name() << endl;
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NetFF*ff = new NetFF(top->scope(), a->name(),
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a->sig()->vector_width());
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hookup_DFF_CE(ff, d, pclk, ce, a, rval_pinoffset);
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des->add_node(ff);
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}
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rval_pinoffset += a->lwidth();
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}
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des->delete_process(top);
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}
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static syn_token_t*first_ = 0;
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static syn_token_t*last_ = 0;
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static syn_token_t*ptr_ = 0;
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/*
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* The match class is used to take a process and turn it into a stream
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* of tokens. This stream is used by the yylex function to feed tokens
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* to the parser.
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*/
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struct tokenize : public proc_match_t {
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tokenize() { }
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~tokenize() { }
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int assign(NetAssign*dev)
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{
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syn_token_t*cur;
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cur = new syn_token_t;
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// Bit Muxes can't be synthesized (yet), but it's too much
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// work to detect them now.
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// cur->token = dev->l_val(0)->bmux() ? S_ASSIGN_MUX : S_ASSIGN;
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cur->token = S_ASSIGN;
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cur->assign = dev;
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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return 0;
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}
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int assign_nb(NetAssignNB*dev)
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{
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syn_token_t*cur;
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cur = new syn_token_t;
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// Bit Muxes can't be synthesized (yet), but it's too much
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// work to detect them now.
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// cur->token = dev->l_val(0)->bmux() ? S_ASSIGN_MUX : S_ASSIGN;
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cur->token = S_ASSIGN;
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cur->assign = dev;
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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return 0;
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}
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int condit(NetCondit*dev)
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{
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syn_token_t*cur;
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cur = new syn_token_t;
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cur->token = S_IF;
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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cur = new syn_token_t;
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cur->token = S_EXPR;
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cur->expr = dev->expr();
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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/* Because synthesis is broken this is needed to prevent
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* a seg. fault. */
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if (!dev->if_clause()) return 0;
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dev -> if_clause() -> match_proc(this);
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if (dev->else_clause()) {
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cur = new syn_token_t;
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cur->token = S_ELSE;
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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dev -> else_clause() -> match_proc(this);
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}
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cur = new syn_token_t;
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cur->token = ';';
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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return 0;
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}
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int event_wait(NetEvWait*dev)
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{
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syn_token_t*cur;
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cur = new syn_token_t;
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cur->token = '@';
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cur->evwait = dev;
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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cur = new syn_token_t;
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cur->token = '(';
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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for (unsigned idx = 0; idx < dev->nevents(); idx += 1) {
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cur = new syn_token_t;
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cur->token = S_EVENT;
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cur->event = dev->event(idx);
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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}
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cur = new syn_token_t;
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cur->token = ')';
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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dev -> statement() -> match_proc(this);
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cur = new syn_token_t;
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cur->token = ';';
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cur->next_ = 0;
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last_->next_ = cur;
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last_ = cur;
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return 0;
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}
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};
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static void syn_start_process(NetProcTop*t)
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{
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first_ = new syn_token_t;
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last_ = first_;
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ptr_ = first_;
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first_->token = (t->type() == IVL_PR_ALWAYS)? S_ALWAYS : S_INITIAL;
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first_->top = t;
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first_->next_ = 0;
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tokenize go;
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t -> statement() -> match_proc(&go);
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}
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static void syn_done_process()
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{
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while (first_) {
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syn_token_t*cur = first_;
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first_ = cur->next_;
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delete cur;
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}
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}
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static int yylex()
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{
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if (ptr_ == 0) {
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yylval = 0;
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return 0;
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}
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yylval = ptr_;
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ptr_ = ptr_->next_;
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return yylval->token;
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}
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struct syn_rules_f : public functor_t {
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~syn_rules_f() { }
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void process(class Design*des, class NetProcTop*top)
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{
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/* If the scope that contains this process as a cell
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attribute attached to it, then skip synthesis. */
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if (top->scope()->attribute(perm_string::literal("ivl_synthesis_cell")).len() > 0)
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return;
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syn_start_process(top);
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yyparse();
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syn_done_process();
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}
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};
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void syn_rules(Design*d)
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{
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des_ = d;
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syn_rules_f obj;
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des_->functor(&obj);
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}
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static void yyerror(const char*)
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{
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}
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