452 lines
12 KiB
C++
452 lines
12 KiB
C++
/*
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* Copyright (c) 2004-2021 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# define __STDC_LIMIT_MACROS
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# include "compile.h"
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# include "part.h"
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# include <cstdlib>
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# include <climits>
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# include <stdint.h>
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# include <iostream>
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# include <cassert>
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using namespace std;
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struct vvp_fun_part_state_s {
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vvp_fun_part_state_s() {}
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vvp_vector4_t bits;
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};
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vvp_fun_part::vvp_fun_part(unsigned base, unsigned wid)
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: base_(base), wid_(wid)
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{
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}
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vvp_fun_part::~vvp_fun_part()
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{
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}
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vvp_fun_part_sa::vvp_fun_part_sa(unsigned base, unsigned wid)
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: vvp_fun_part(base, wid)
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{
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net_ = 0;
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}
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vvp_fun_part_sa::~vvp_fun_part_sa()
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{
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}
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void vvp_fun_part_sa::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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vvp_context_t)
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{
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assert(port.port() == 0);
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vvp_vector4_t tmp (bit, base_, wid_);
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if (val_ .eeq( tmp ))
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return;
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val_ = tmp;
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if (net_ == 0) {
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net_ = port.ptr();
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schedule_functor(this);
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}
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}
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/*
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* Handle the case that the part select node is actually fed by a part
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* select assignment. It's not exactly clear what might make this
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* happen, but is does seem to happen and this should have well
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* defined behavior.
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*/
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void vvp_fun_part_sa::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t)
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{
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vvp_vector4_t tmp (vwid, BIT4_Z);
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tmp.set_vec(base_, val_);
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tmp.set_vec(base, bit);
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recv_vec4(port, tmp, 0);
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}
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void vvp_fun_part_sa::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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ptr->send_vec4(val_, 0);
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}
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vvp_fun_part_aa::vvp_fun_part_aa(unsigned base, unsigned wid)
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: vvp_fun_part(base, wid)
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{
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context_scope_ = vpip_peek_context_scope();
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context_idx_ = vpip_add_item_to_context(this, context_scope_);
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}
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vvp_fun_part_aa::~vvp_fun_part_aa()
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{
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}
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void vvp_fun_part_aa::alloc_instance(vvp_context_t context)
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{
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vvp_set_context_item(context, context_idx_, new vvp_vector4_t);
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}
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void vvp_fun_part_aa::reset_instance(vvp_context_t context)
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{
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vvp_vector4_t*val = static_cast<vvp_vector4_t*>
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(vvp_get_context_item(context, context_idx_));
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val->set_to_x();
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}
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#ifdef CHECK_WITH_VALGRIND
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void vvp_fun_part_aa::free_instance(vvp_context_t context)
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{
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vvp_vector4_t*val = static_cast<vvp_vector4_t*>
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(vvp_get_context_item(context, context_idx_));
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delete val;
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}
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#endif
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void vvp_fun_part_aa::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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vvp_context_t context)
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{
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if (context) {
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assert(port.port() == 0);
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vvp_vector4_t*val = static_cast<vvp_vector4_t*>
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(vvp_get_context_item(context, context_idx_));
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vvp_vector4_t tmp (wid_, BIT4_X);
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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if (idx + base_ < bit.size())
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tmp.set_bit(idx, bit.value(base_+idx));
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}
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if (!val->eeq( tmp )) {
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*val = tmp;
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port.ptr()->send_vec4(tmp, context);
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}
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} else {
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context = context_scope_->live_contexts;
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while (context) {
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recv_vec4(port, bit, context);
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context = vvp_get_next_context(context);
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}
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}
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}
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/*
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* Handle the case that the part select node is actually fed by a part
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* select assignment. It's not exactly clear what might make this
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* happen, but is does seem to happen and this should have well
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* defined behavior.
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*/
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void vvp_fun_part_aa::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t context)
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{
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if (context) {
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vvp_vector4_t*val = static_cast<vvp_vector4_t*>
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(vvp_get_context_item(context, context_idx_));
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vvp_vector4_t tmp (vwid, BIT4_Z);
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tmp.set_vec(base_, *val);
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tmp.set_vec(base, bit);
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recv_vec4(port, tmp, context);
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} else {
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context = context_scope_->live_contexts;
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while (context) {
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recv_vec4_pv(port, bit, base, vwid, context);
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context = vvp_get_next_context(context);
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}
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}
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}
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vvp_fun_part_pv::vvp_fun_part_pv(unsigned b, unsigned w, unsigned v)
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: base_(b), wid_(w), vwid_(v)
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{
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}
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vvp_fun_part_pv::~vvp_fun_part_pv()
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{
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}
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void vvp_fun_part_pv::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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vvp_context_t context)
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{
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assert(port.port() == 0);
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if (bit.size() != wid_) {
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cerr << "internal error: part_pv data mismatch. "
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<< "base_=" << base_ << ", wid_=" << wid_
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<< ", vwid_=" << vwid_ << ", bit=" << bit
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<< endl;
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}
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assert(bit.size() == wid_);
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port.ptr()->send_vec4_pv(bit, base_, vwid_, context);
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}
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void vvp_fun_part_pv::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t ctx)
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{
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assert(port.port() == 0);
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assert(base + bit.size() <= vwid);
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assert(vwid == wid_);
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vvp_vector4_t tmp(wid_, BIT4_Z);
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tmp.set_vec(base, bit);
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port.ptr()->send_vec4_pv(tmp, base_, vwid_, ctx);
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}
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void vvp_fun_part_pv::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)
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{
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assert(port.port() == 0);
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if (bit.size() != wid_) {
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cerr << "internal error: part_pv (strength-aware) data mismatch. "
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<< "base_=" << base_ << ", wid_=" << wid_
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<< ", vwid_=" << vwid_ << ", bit=" << bit
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<< endl;
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}
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assert(bit.size() == wid_);
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port.ptr()->send_vec8_pv(bit, base_, vwid_);
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}
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vvp_fun_part_var::vvp_fun_part_var(unsigned w, bool is_signed)
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: wid_(w), is_signed_(is_signed)
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{
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}
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vvp_fun_part_var::~vvp_fun_part_var()
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{
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}
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bool vvp_fun_part_var::recv_vec4_(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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int&base, vvp_vector4_t&source,
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vvp_vector4_t&ref)
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{
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int32_t tmp;
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switch (port.port()) {
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case 0:
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source = bit;
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break;
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case 1:
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// INT_MIN is before the vector and is used to
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// represent a 'bx value on the select input.
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// It is also used to guard against 32 bit
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// unsigned -> signed address overflow / wrap around.
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if (!vector4_to_value(bit, tmp, is_signed_) || (!is_signed_ && tmp < 0))
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tmp = INT32_MIN;
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if (static_cast<int>(tmp) == base) return false;
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base = tmp;
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break;
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default:
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fprintf(stderr, "Unsupported port type %u.\n", port.port());
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assert(0);
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break;
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}
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vvp_vector4_t res (wid_);
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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int adr = base+idx;
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if (adr < 0) continue;
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if ((unsigned)adr >= source.size()) break;
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res.set_bit(idx, source.value((unsigned)adr));
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}
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if (! ref.eeq(res)) {
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ref = res;
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return true;
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}
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return false;
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}
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vvp_fun_part_var_sa::vvp_fun_part_var_sa(unsigned w, bool is_signed)
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: vvp_fun_part_var(w, is_signed), base_(0)
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{
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}
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vvp_fun_part_var_sa::~vvp_fun_part_var_sa()
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{
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}
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void vvp_fun_part_var_sa::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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vvp_context_t)
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{
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if (recv_vec4_(port, bit, base_, source_, ref_)) {
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port.ptr()->send_vec4(ref_, 0);
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}
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}
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void vvp_fun_part_var_sa::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t)
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{
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vvp_vector4_t tmp = source_;
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if (tmp.size() == 0)
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tmp = vvp_vector4_t(vwid);
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assert(tmp.size() == vwid);
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tmp.set_vec(base, bit);
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recv_vec4(port, tmp, 0);
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}
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struct vvp_fun_part_var_state_s {
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vvp_fun_part_var_state_s() : base(0) { }
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int base;
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vvp_vector4_t source;
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vvp_vector4_t ref;
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};
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vvp_fun_part_var_aa::vvp_fun_part_var_aa(unsigned w, bool is_signed)
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: vvp_fun_part_var(w, is_signed)
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{
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context_scope_ = vpip_peek_context_scope();
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context_idx_ = vpip_add_item_to_context(this, context_scope_);
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}
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vvp_fun_part_var_aa::~vvp_fun_part_var_aa()
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{
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}
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void vvp_fun_part_var_aa::alloc_instance(vvp_context_t context)
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{
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vvp_set_context_item(context, context_idx_, new vvp_fun_part_var_state_s);
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}
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void vvp_fun_part_var_aa::reset_instance(vvp_context_t context)
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{
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vvp_fun_part_var_state_s*state = static_cast<vvp_fun_part_var_state_s*>
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(vvp_get_context_item(context, context_idx_));
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state->base = 0;
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state->source.set_to_x();
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state->ref.set_to_x();
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}
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#ifdef CHECK_WITH_VALGRIND
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void vvp_fun_part_var_aa::free_instance(vvp_context_t context)
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{
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vvp_fun_part_var_state_s*state = static_cast<vvp_fun_part_var_state_s*>
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(vvp_get_context_item(context, context_idx_));
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delete state;
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}
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#endif
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void vvp_fun_part_var_aa::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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vvp_context_t context)
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{
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if (context) {
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vvp_fun_part_var_state_s*state = static_cast<vvp_fun_part_var_state_s*>
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(vvp_get_context_item(context, context_idx_));
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if (recv_vec4_(port, bit, state->base, state->source, state->ref)) {
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port.ptr()->send_vec4(state->ref, context);
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}
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} else {
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context = context_scope_->live_contexts;
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while (context) {
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recv_vec4(port, bit, context);
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context = vvp_get_next_context(context);
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}
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}
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}
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void vvp_fun_part_var_aa::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t context)
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{
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if (context) {
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vvp_fun_part_var_state_s*state = static_cast<vvp_fun_part_var_state_s*>
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(vvp_get_context_item(context, context_idx_));
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vvp_vector4_t tmp = state->source;
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if (tmp.size() == 0)
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tmp = vvp_vector4_t(vwid);
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assert(tmp.size() == vwid);
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tmp.set_vec(base, bit);
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recv_vec4(port, tmp, context);
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} else {
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context = context_scope_->live_contexts;
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while (context) {
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recv_vec4(port, bit, context);
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context = vvp_get_next_context(context);
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}
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}
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}
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/*
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* Given a node functor, create a network node and link it into the
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* netlist. This form assumes nodes with a single input.
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*/
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void link_node_1(char*label, char*source, vvp_net_fun_t*fun)
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{
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vvp_net_t*net = new vvp_net_t;
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net->fun = fun;
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define_functor_symbol(label, net);
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free(label);
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input_connect(net, 0, source);
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}
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void compile_part_select(char*label, char*source,
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unsigned base, unsigned wid)
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{
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vvp_fun_part*fun = 0;
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if (vpip_peek_current_scope()->is_automatic()) {
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fun = new vvp_fun_part_aa(base, wid);
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} else {
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fun = new vvp_fun_part_sa(base, wid);
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}
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link_node_1(label, source, fun);
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}
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void compile_part_select_pv(char*label, char*source,
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unsigned base, unsigned wid,
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unsigned vector_wid)
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{
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vvp_fun_part_pv*fun = new vvp_fun_part_pv(base, wid, vector_wid);
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link_node_1(label, source, fun);
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}
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void compile_part_select_var(char*label, char*source, char*var,
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unsigned wid, bool is_signed)
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{
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vvp_fun_part_var*fun = 0;
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if (vpip_peek_current_scope()->is_automatic()) {
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fun = new vvp_fun_part_var_aa(wid, is_signed);
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} else {
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fun = new vvp_fun_part_var_sa(wid, is_signed);
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}
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vvp_net_t*net = new vvp_net_t;
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net->fun = fun;
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define_functor_symbol(label, net);
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free(label);
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input_connect(net, 0, source);
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input_connect(net, 1, var);
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}
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