61 lines
1.8 KiB
Plaintext
61 lines
1.8 KiB
Plaintext
:ivl_version "12.0" "vec4-stack";
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:vpi_module "system";
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; Copyright (c) 2001-2015 Stephen Williams (steve@icarus.com)
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 2 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License along
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; with this program; if not, write to the Free Software Foundation, Inc.,
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; 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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; This example shows how to wire a simple adder. The code below is like what
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; would be generated from the following Verilog program:
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;
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; module main;
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; reg [3:0] A, B;
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; wire [3:0] Q = A + B;
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;
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; initial begin
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; A = 2;
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; B = 3;
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; #1 $display("%b + %b = %b", A, B, Q);
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; end
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; endmodule
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;
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; Notice the use of the .arith/sum statement, including the specification
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; of the width (4 bits) and the order that the bits of the operands are
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; passed to the statement.
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S_main .scope module, "main" "main" 0 0;
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A .var "A", 3 0;
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B .var "B", 3 0;
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Q .net "Q", 3 0, add;
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add .arith/sum 4, A, B;
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start %pushi/vec4 2, 0, 4; Push a 4 bit value (2) on the stack
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%store/vec4 A, 0, 4;
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%pushi/vec4 3, 0, 4; Ditto except the value is 3
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%store/vec4 B, 0, 4;
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%delay 1, 0;
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%vpi_call 0 0 "$display", "%b + %b == %b", A, B, Q {0 0 0};
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%end;
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.thread start;
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:file_names 2;
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"N/A";
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"<interactive>";
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