53 lines
1.7 KiB
Plaintext
53 lines
1.7 KiB
Plaintext
:ivl_version "12.0" "vec4-stack";
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:vpi_module "system";
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; Copyright (c) 2001-2015 Stephen Williams (steve@icarus.com)
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 2 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License along
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; with this program; if not, write to the Free Software Foundation, Inc.,
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; 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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; This example slightly extends the hello.vvp example by adding the
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; set and display of a reg variable. The Verilog source that would
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; make this might be:
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;
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; module main;
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; reg [3:0] value1;
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; initial begin
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; value1 = 1;
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; $display("value = %b", value1);
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; end
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; endmodule
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;
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; Notice that the var "value1" is placed into the "main" scope simply
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; by having main current when the .var statement is compiled. And also
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; notice that the Vmain.value1 label is automatically converted to a
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; vpiHandle by the compiler when the %vpi_call statement is compiled.
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Smain .scope module, "main" "main" 0 0;
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Vmain.value1 .var "value1", 3 0;
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T00 %pushi/vec4 1, 0, 4; Push a 4 bit value (1) on the stack
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%store/vec4 Vmain.value1, 0, 4;
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%vpi_call 0 0 "$display", "value = %b", Vmain.value1 {0 0 0};
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%end;
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.thread T00;
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:file_names 2;
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"N/A";
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"<interactive>";
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