iverilog/vvp/examples/edge.vvp

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:ivl_version "12.0" "vec4-stack";
:vpi_module "system";
; Copyright (c) 2001-2015 Stephen Williams (steve@icarus.com)
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License along
; with this program; if not, write to the Free Software Foundation, Inc.,
; 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
; This example tests the operation of a simple posedge event. The module
; that would generate code like this would be:
;
; module main;
; reg a;
;
; initial begin
; a = 0;
; #1 a = 1;
; end
;
; always @(posedge a) $display("Got a posedge.");
;
; endmodule
main .scope module, "main" "main" 0 0;
V_main.a .var "a", 0 0;
V_main.b .event posedge, V_main.a;
code %pushi/vec4 0, 0, 1;
%store/vec4 V_main.a, 0, 1;
%delay 1, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 V_main.a, 0, 1;
%end;
.thread code;
loop %wait V_main.b;
%vpi_call 0 0 "$display", "Got a posedge." {0 0 0};
%jmp loop;
.thread loop;
:file_names 2;
"N/A";
"<interactive>";