93 lines
3.2 KiB
C++
93 lines
3.2 KiB
C++
/*
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* Copyright (c) 2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "priv.h"
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# include "nex_data.h"
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# include <cassert>
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using namespace std;
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int print_lpm_ff(FILE*fd, ivl_lpm_t net)
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{
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int errors = 0;
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ivl_nexus_t nex_q = ivl_lpm_q(net);
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blif_nex_data_t*ned_q = blif_nex_data_t::get_nex_data(nex_q);
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ivl_nexus_t nex_d = ivl_lpm_data(net,0);
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blif_nex_data_t*ned_d = blif_nex_data_t::get_nex_data(nex_d);
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ivl_nexus_t nex_c = ivl_lpm_clk(net);
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blif_nex_data_t*ned_c = blif_nex_data_t::get_nex_data(nex_c);
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ivl_nexus_t nex_ce = ivl_lpm_enable(net);
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blif_nex_data_t*ned_ce = nex_ce? blif_nex_data_t::get_nex_data(nex_ce) : 0;
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if (ivl_lpm_async_clr(net)) {
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errors += 1;
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fprintf(stderr, "%s:%u: sorry: blif: Asynchronous clear not implemented yet\n",
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ivl_lpm_file(net), ivl_lpm_lineno(net));
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}
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if (ivl_lpm_async_set(net)) {
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errors += 1;
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fprintf(stderr, "%s:%u: sorry: blif: Asynchronous set not implemented yet\n",
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ivl_lpm_file(net), ivl_lpm_lineno(net));
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}
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fprintf(fd, "# IVL_LPM_FF: width=%u, Q=%s, D=%s, C=%s, CE=%s\n",
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ivl_lpm_width(net), ned_q->get_name(), ned_d->get_name(), ned_c->get_name(), ned_ce? ned_ce->get_name() : "N/A");
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if (ned_ce) {
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// If there is a clock-enable, rewrite this in a form
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// that blif can accept. Transform this:
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//
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// always @(posedge C) if (CE) Q <= D;
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//
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// to this:
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//
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// always @(posedge C) Q <= CE? D : Q;
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//
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// In ASIC-land, this is probably OK.
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for (unsigned wid = 0 ; wid < ivl_lpm_width(net) ; wid += 1) {
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fprintf(fd, ".names %s%s %s%s %s%s %s%s/EN\n"
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"0-1 1\n"
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"11- 1\n",
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ned_ce->get_name(), ned_ce->get_name_index(0),
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ned_d ->get_name(), ned_d ->get_name_index(wid),
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ned_q ->get_name(), ned_q ->get_name_index(wid),
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ned_d ->get_name(), ned_d ->get_name_index(wid));
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fprintf(fd, ".latch %s%s/EN %s%s re %s%s 3\n",
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ned_d->get_name(), ned_d->get_name_index(wid),
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ned_q->get_name(), ned_q->get_name_index(wid),
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ned_c->get_name(), ned_c->get_name_index(0));
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}
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} else {
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for (unsigned wid = 0 ; wid < ivl_lpm_width(net) ; wid += 1) {
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fprintf(fd, ".latch %s%s %s%s re %s%s 3\n",
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ned_d->get_name(), ned_d->get_name_index(wid),
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ned_q->get_name(), ned_q->get_name_index(wid),
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ned_c->get_name(), ned_c->get_name_index(0));
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}
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}
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return errors;
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}
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