22 lines
343 B
Verilog
22 lines
343 B
Verilog
// Check that an ANSI-style UDP reg output can have an initializer.
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primitive udp_ansi_initial_reg (output reg o = 1'b0, input i);
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table
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0 : ? : 0;
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1 : ? : 1;
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endtable
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endprimitive
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module test;
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reg i;
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wire o;
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udp_ansi_initial_reg i_udp(o, i);
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initial begin
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i = 1'b0;
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#1;
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$display("PASSED");
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end
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endmodule
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