38 lines
574 B
Verilog
38 lines
574 B
Verilog
// Check that a class property can have the same name as the class.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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int C;
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function int get;
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return C;
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endfunction
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endclass
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C obj;
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initial begin
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obj = new;
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obj.C = 23;
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`check(obj.get(), 23);
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`check(obj.C, 23);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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