32 lines
592 B
Verilog
32 lines
592 B
Verilog
// Check that unary real minus preserves the sign of zero.
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module test;
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reg failed;
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real zero;
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real result;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %h, got %h", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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initial begin
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failed = 1'b0;
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zero = 0.0;
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result = -zero;
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`check($realtobits(result), 64'h8000000000000000);
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result = -result;
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`check($realtobits(result), 64'h0000000000000000);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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