47 lines
793 B
Verilog
47 lines
793 B
Verilog
// Check that non-blocking event control repeat counts can use automatic terms.
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module test;
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reg clk;
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reg failed;
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reg [3:0] result;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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task automatic schedule_update;
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input integer count;
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begin
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result <= repeat(count) @(posedge clk) 4'ha;
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end
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endtask
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always #5 clk = ~clk;
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initial begin
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clk = 1'b0;
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failed = 1'b0;
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result = 4'h0;
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schedule_update(2);
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@(posedge clk);
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#1;
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`check(result, 4'h0);
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@(posedge clk);
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#1;
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`check(result, 4'ha);
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if (!failed) begin
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$display("PASSED");
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end
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$finish;
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end
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endmodule
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