iverilog/ivtest/gold/pr1866215b.gold

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./ivltests/pr1866215b.v:26: warning: Port 1 (CH) of module C expects 7 bit(s), given 6.
./ivltests/pr1866215b.v:26: : Padding 1 high bits of the port.
./ivltests/pr1866215b.v:26: warning: Port 3 (SH) of module C expects 8 bit(s), given 7.
./ivltests/pr1866215b.v:26: : Padding 1 high bits of the port.
./ivltests/pr1866215b.v:10: warning: Port 1 (CH) of module B expects 6 bit(s), given 16.
./ivltests/pr1866215b.v:10: : Pruning 10 high bits of the expression.
./ivltests/pr1866215b.v:10: warning: Port 3 (SH) of module B expects 7 bit(s), given 16.
./ivltests/pr1866215b.v:10: : Pruning 9 high bits of the expression.
CH=3f, CL=55555555, SH=7f, SL=aaaaaaaa