142 lines
3.8 KiB
Bash
Executable File
142 lines
3.8 KiB
Bash
Executable File
#!/bin/sh
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#
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# This source code is free software; you can redistribute it
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# and/or modify it in source code form under the terms of the GNU
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# Library General Public License as published by the Free Software
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# Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU Library General Public License for more details.
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#
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# You should have received a copy of the GNU Library General Public
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# License along with this program; if not, write to the Free
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# Software Foundation, Inc.,
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# 59 Temple Place - Suite 330
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# Boston, MA 02111-1307, USA
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#
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#ident "$Id: fpga_reg.sh,v 1.5 2004/01/13 03:37:04 stevewilliams Exp $"
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# This script runs the synthesis tests listed in the fpga_reg.list
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# list file. The script uses Icarus Verilog from the path, and also
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# gets ngdbuild and ngd2ver from the path. The XILINX variable needs
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# to point to the XILINX install directory so that the simprims
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# can be found. The run test uses these to generate a simulation
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# from the synthesized file.
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#
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# Usage: sh ./fpga_reg.sh [select]
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#
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# If there is no select, then run all the tests. If there is a select,
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# then only run the tests that match the select regular expression.
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#
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# This is a diff command for comparing log with gold files.
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diff="diff --strip-trailing-cr -aq"
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# This is the output file.
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status_file=fpga_reg.txt
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true > $status_file
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if ! test -d fpga_log
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then
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mkdir fpga_log
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fi
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if ! test -d fpga_tmp
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then
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mkdir fpga_tmp
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fi
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if test "X$1" = "X"; then
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match='.*'
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else
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match="$1"
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fi
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cat fpga_reg.list |
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sed -e 's/#.*//' |
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while read test tb arch part gold junk
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do
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if test "X$test" = "X" -o 0 = `expr X$test : X$match`
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then
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: skip a comment
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else
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if test "X$part" != "X-"
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then
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part="-ppart=$part"
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else
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part=
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fi
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true > fpga_log/$test-$arch.log 2>&1
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EDIF="$test-$arch.edf"
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synth="iverilog -ofpga_tmp/$EDIF -tfpga -parch=$arch $part $test.v"
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echo "synth=$synth"
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eval "$synth" > fpga_log/$test-$arch-synth.log 2>&1
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if test $? != 0
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then
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echo "$test-$arch: FAILED -- Synthesis error" >> $status_file
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continue
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fi
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ngdbuild="ngdbuild $EDIF $test.ngd"
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echo "ngdbuild=$ngdbuild"
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(eval "cd fpga_tmp; $ngdbuild") > fpga_log/$test-$arch-build.log 2>&1
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if test $? != 0
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then
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echo "$test-$arch: FAILED -- ngdbuild error" >> $status_file
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continue
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fi
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ngd2ver="ngd2ver -w $test.ngd $test.edf.v"
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echo "ngd2ver=$ngd2ver"
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(eval "cd fpga_tmp; $ngd2ver") > fpga_log/$test-$arch-ngd2ver.log 2>&1
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if test $? != 0
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then
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echo "$test-$arch: FAILED -- ngd2ver error" >> $status_file
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continue
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fi
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iverilog -oa.out -Ttyp $tb.v fpga_tmp/$test.edf.v $XILINX/verilog/src/glbl.v -y $XILINX/verilog/src/simprims
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if test $? != 0
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then
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echo "$test-$arch: FAILED -- compiling test bench" >> $status_file
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continue
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fi
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vvp a.out > fpga_log/$test-$arch.log 2>&1
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if test "X$gold" != "X-" ; then
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if $diff $gold fpga_log/$test-$arch.log > /dev/null
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then
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echo "$test-$arch: PASSED -- Correct output." >> $status_file
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else
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echo "$test-$arch: FAILED -- Incorrect output." >> $status_file
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fi
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else
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if grep -a -q PASSED fpga_log/$test-$arch.log
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then
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echo "$test-$arch: PASSED" >> $status_file
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else
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echo "$test-$arch: FAILED" >> $status_file
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fi
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fi
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rm a.out
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fi
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done
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PASSED=`grep ': PASSED' $status_file | wc -l`
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FAILED=`grep ': FAILED' $status_file | wc -l`
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echo "PASSED=$PASSED, FAILED=$FAILED" >> $status_file
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# $Log: fpga_reg.sh,v $
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# Revision 1.5 2004/01/13 03:37:04 stevewilliams
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# Cope with dos line-ends while comparing gold files.
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#
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# Revision 1.4 2003/04/01 05:58:36 stevewilliams
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# Add a select argument.
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#
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