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<section id="viewing-waveforms">
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<h1>Viewing Waveforms<a class="headerlink" href="#viewing-waveforms" title="Link to this heading">¶</a></h1>
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||
<p>To view waveforms, either GTKWave or Surfer can be used.</p>
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||
<p>GTKWave is a waveform viewer based on the GTK library. This viewer supports
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VCD, FST, LXT, and LXT2 formats for waveform dumps. GTKWave is available on GitHub
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||
<a class="reference external" href="https://github.com/gtkwave/gtkwave">here</a>. Most Linux distributions already
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include gtkwave prepackaged and there are binaries for Windows available.</p>
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||
<img alt="../_images/GTKWave_Example2.png" src="../_images/GTKWave_Example2.png" />
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||
<p>Surfer is a waveform viewer based on the Rust egui library. This viewer supports
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||
VCD and FST formats for waveform dumps. Surfer is available on GitLab
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||
<a class="reference external" href="https://gitlab.com/surfer-project/surfer">here</a>. It runs on Windows, Linux,
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||
and MacOS, but can also run in a <a class="reference external" href="https://app.surfer-project.org/">web browser</a>
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||
and there is a VS Code
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<a class="reference external" href="https://marketplace.visualstudio.com/items?itemName=surfer-project.surfer">extension</a>.</p>
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||
<section id="generating-waveform-dump-files-for-viewing">
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||
<h2>Generating waveform dump files for viewing<a class="headerlink" href="#generating-waveform-dump-files-for-viewing" title="Link to this heading">¶</a></h2>
|
||
<p>Waveform dumps are written by the Icarus Verilog runtime program vvp. The user
|
||
uses $dumpfile and $dumpvars system tasks to enable waveform dumping, then the
|
||
vvp runtime takes care of the rest. The output is written into the file
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||
specified by the $dumpfile system task. If the $dumpfile call is absent, the
|
||
compiler will choose the file name dump.vcd, dump.lxt, dump.lxt2, or dump.fst,
|
||
depending on runtime flags. The example below dumps everything in and below
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||
the test module:</p>
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||
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="c1">// Do this in your test bench</span>
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</span><span data-line="2">
|
||
</span><span data-line="3"><span class="k">initial</span>
|
||
</span><span data-line="4"><span class="k">begin</span>
|
||
</span><span data-line="5"><span class="w"> </span><span class="n">$dumpfile</span><span class="p">(</span><span class="s">"test.vcd"</span><span class="p">);</span>
|
||
</span><span data-line="6"><span class="w"> </span><span class="n">$dumpvars</span><span class="p">(</span><span class="mh">0</span><span class="p">,</span><span class="n">test</span><span class="p">);</span>
|
||
</span><span data-line="7"><span class="k">end</span>
|
||
</span></pre></div>
|
||
</div>
|
||
<p>By default, the vvp runtime will generate VCD dump output. This is the default
|
||
because it is the most portable. However, when using gtkwave, the FST output
|
||
format is faster and most compact. Use the “-fst”, “-lxt”, or “-lxt2” extended
|
||
argument to activate FST, LXT, or LXT2 output, respectively. For example, if
|
||
your compiled output is written into the file “foo.vvp”, the command:</p>
|
||
<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="gp">% </span>vvp<span class="w"> </span>foo.vvp<span class="w"> </span>-fst<span class="w"> </span><other-plusargs>
|
||
</span></pre></div>
|
||
</div>
|
||
<p>will cause the dumpfile output to be written in FST format. Absent any
|
||
specific $dumpfile command, this file will be called dump.fst, which can be
|
||
viewed with GTKWave using the command:</p>
|
||
<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="gp">% </span>gtkwave<span class="w"> </span>dump.fst
|
||
</span></pre></div>
|
||
</div>
|
||
</section>
|
||
<section id="a-working-example">
|
||
<h2>A Working Example<a class="headerlink" href="#a-working-example" title="Link to this heading">¶</a></h2>
|
||
<p>First, the design itself:</p>
|
||
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="k">module</span><span class="w"> </span><span class="n">counter</span><span class="p">(</span><span class="n">out</span><span class="p">,</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">);</span>
|
||
</span><span data-line="2">
|
||
</span><span data-line="3"><span class="w"> </span><span class="k">parameter</span><span class="w"> </span><span class="n">WIDTH</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">8</span><span class="p">;</span>
|
||
</span><span data-line="4">
|
||
</span><span data-line="5"><span class="w"> </span><span class="k">output</span><span class="w"> </span><span class="p">[</span><span class="n">WIDTH</span><span class="o">-</span><span class="mh">1</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">out</span><span class="p">;</span>
|
||
</span><span data-line="6"><span class="w"> </span><span class="k">input</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">;</span>
|
||
</span><span data-line="7">
|
||
</span><span data-line="8"><span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="n">WIDTH</span><span class="o">-</span><span class="mh">1</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">out</span><span class="p">;</span>
|
||
</span><span data-line="9"><span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">;</span>
|
||
</span><span data-line="10">
|
||
</span><span data-line="11"><span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">@(</span><span class="k">posedge</span><span class="w"> </span><span class="n">clk</span><span class="p">)</span>
|
||
</span><span data-line="12"><span class="w"> </span><span class="n">out</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="n">out</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
||
</span><span data-line="13">
|
||
</span><span data-line="14"><span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">@</span><span class="n">reset</span>
|
||
</span><span data-line="15"><span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">reset</span><span class="p">)</span>
|
||
</span><span data-line="16"><span class="w"> </span><span class="k">assign</span><span class="w"> </span><span class="n">out</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="17"><span class="w"> </span><span class="k">else</span>
|
||
</span><span data-line="18"><span class="w"> </span><span class="k">deassign</span><span class="w"> </span><span class="n">out</span><span class="p">;</span>
|
||
</span><span data-line="19">
|
||
</span><span data-line="20"><span class="k">endmodule</span><span class="w"> </span><span class="c1">// counter</span>
|
||
</span></pre></div>
|
||
</div>
|
||
<p>Then the simulation file:</p>
|
||
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="k">module</span><span class="w"> </span><span class="n">test</span><span class="p">;</span>
|
||
</span><span data-line="2">
|
||
</span><span data-line="3"><span class="w"> </span><span class="cm">/* Make a reset that pulses once. */</span>
|
||
</span><span data-line="4"><span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="5"><span class="w"> </span><span class="k">initial</span><span class="w"> </span><span class="k">begin</span>
|
||
</span><span data-line="6"><span class="w"> </span><span class="n">$dumpfile</span><span class="p">(</span><span class="s">"test.vcd"</span><span class="p">);</span>
|
||
</span><span data-line="7"><span class="w"> </span><span class="n">$dumpvars</span><span class="p">(</span><span class="mh">0</span><span class="p">,</span><span class="n">test</span><span class="p">);</span>
|
||
</span><span data-line="8">
|
||
</span><span data-line="9"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">17</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
||
</span><span data-line="10"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">11</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="11"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">29</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
||
</span><span data-line="12"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">5</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="13"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">513</span><span class="w"> </span><span class="nb">$finish</span><span class="p">;</span>
|
||
</span><span data-line="14"><span class="w"> </span><span class="k">end</span>
|
||
</span><span data-line="15">
|
||
</span><span data-line="16"><span class="w"> </span><span class="cm">/* Make a regular pulsing clock. */</span>
|
||
</span><span data-line="17"><span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="18"><span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">#</span><span class="mh">1</span><span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="o">!</span><span class="n">clk</span><span class="p">;</span>
|
||
</span><span data-line="19">
|
||
</span><span data-line="20"><span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">7</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">value</span><span class="p">;</span>
|
||
</span><span data-line="21"><span class="w"> </span><span class="n">counter</span><span class="w"> </span><span class="n">c1</span><span class="w"> </span><span class="p">(</span><span class="n">value</span><span class="p">,</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">);</span>
|
||
</span><span data-line="22">
|
||
</span><span data-line="23"><span class="w"> </span><span class="k">initial</span>
|
||
</span><span data-line="24"><span class="w"> </span><span class="nb">$monitor</span><span class="p">(</span><span class="s">"At time %t, value = %h (%0d)"</span><span class="p">,</span>
|
||
</span><span data-line="25"><span class="w"> </span><span class="nb">$time</span><span class="p">,</span><span class="w"> </span><span class="n">value</span><span class="p">,</span><span class="w"> </span><span class="n">value</span><span class="p">);</span>
|
||
</span><span data-line="26"><span class="k">endmodule</span><span class="w"> </span><span class="c1">// test</span>
|
||
</span></pre></div>
|
||
</div>
|
||
<p>Compile, run, and view waveforms with GTKWave using these commands:</p>
|
||
<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="gp">% </span>iverilog<span class="w"> </span>-o<span class="w"> </span>dsn<span class="w"> </span>counter_tb.v<span class="w"> </span>counter.v
|
||
</span><span data-line="2"><span class="gp">% </span>vvp<span class="w"> </span>dsn
|
||
</span><span data-line="3"><span class="gp">% </span>gtkwave<span class="w"> </span>test.vcd<span class="w"> </span><span class="p">&</span>
|
||
</span></pre></div>
|
||
</div>
|
||
<p>Click on the ‘test’, then ‘c1’ in the top left box of GTKWave, then drag the
|
||
signals to the Signals box. You will be able to add signals to display,
|
||
scanning by scope.</p>
|
||
</section>
|
||
</section>
|
||
|
||
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