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161 lines
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<section id="verilog-attributes">
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<h1>Verilog Attributes<a class="headerlink" href="#verilog-attributes" title="Link to this heading">¶</a></h1>
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<p>This is a description of the various attributes that the Icarus Verilog tools
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understand. The attributes are attached to objects using the “(* … *)”
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syntax, which is described by the Verilog LRM.</p>
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<p>Attributes that start with “ivl_” are Icarus Verilog specific are are probably
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ignored by other tools.</p>
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<section id="optimizations">
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<h2>Optimizations<a class="headerlink" href="#optimizations" title="Link to this heading">¶</a></h2>
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<ul>
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<li><p>ivl_do_not_elide (snapshot 20140619 or later)</p>
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<p>This applies to signals (i.e. reg, wire, etc.) and tells the optimizer to
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not elide the signal, even if it is not referenced anywhere in the
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design. This is useful if the signal is for some reason only accessed by
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VPI/PLI code.</p>
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</li>
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</ul>
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</section>
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<section id="synthesis">
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<h2>Synthesis<a class="headerlink" href="#synthesis" title="Link to this heading">¶</a></h2>
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<ul>
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<li><p>ivl_synthesis_cell</p>
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<p>Applied to a module definition, this tells the synthesizer that the module
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is a cell. The synthesizer does not descend into synthesis cells, as they
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are assumed to be primitives in the target technology.</p>
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</li>
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<li><p>ivl_synthesis_off</p>
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<p>Attached to an “always” statement, this tells the synthesizer that the
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statement is not to be synthesized. This may be useful, for example, to tell
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the compiler that a stretch of code is test-bench code.</p>
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