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<li class="toctree-l1"><a class="reference internal" href="../releases/index.html">Icarus Verilog Release Notes</a><ul>
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<li class="toctree-l2"><a class="reference internal" href="ivlpp_flags.html">IVLPP - IVL Preprocessor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="vvp_flags.html">VVP Command Line Flags</a></li>
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<li class="toctree-l2"><a class="reference internal" href="vpi.html">Using VPI</a></li>
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<li class="toctree-l1"><a class="reference internal" href="../targets/index.html">The Icarus Verilog Targets</a><ul>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-vvp.html">The vvp Code Generator (-tvvp)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-pal.html">The PAL Code Generator (-tpal)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-sizer.html">The sizer Code Analyzer (-tsizer)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../targets/tgt-verilog.html">The Verilog Code Generator (-tverilog)</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../developer/regression_tests.html">The Regression Test Suite</a></li>
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<li class="toctree-l4"><a class="reference internal" href="../developer/guide/ivl/ivl_target.html">Loadable Target API (ivl_target)</a></li>
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<li class="toctree-l3"><a class="reference internal" href="../developer/guide/vvp/index.html">VVP - Verilog Virtual Processor</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="../developer/guide/vvp/debug.html">Debug Aids For VVP</a></li>
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<li class="toctree-l3"><a class="reference internal" href="../developer/guide/tgt-vvp/tgt-vvp.html">The VVP Target</a></li>
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<li class="toctree-l3"><a class="reference internal" href="../developer/guide/vpi/index.html">VPI in Icarus Verilog</a><ul>
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<li class="toctree-l4"><a class="reference internal" href="../developer/guide/vpi/vpi.html">VPI Modules in Icarus Verilog</a></li>
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<section id="getting-started-with-icarus-verilog">
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<h1>Getting Started With Icarus Verilog<a class="headerlink" href="#getting-started-with-icarus-verilog" title="Link to this heading">¶</a></h1>
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<p>Before getting started with actual examples, here are a few notes on
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conventions. First, command lines and sequences take the same arguments on all
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supported operating environments, including Linux, Windows and the various
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Unix systems. When an example command is shown in a figure, the generic prompt
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character “% “ takes the place of whatever prompt string is appropriate for
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your system. Under Windows, the commands are invoked in a command window.</p>
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<p>Second, when creating a file to hold Verilog code, it is common to use the
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“.v” or the “.vl” suffix. This is not a requirement imposed by Icarus Verilog,
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but a useful convention. Some people also use the suffixes “.ver” or even
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“.vlg”. Examples in this book will use the “.v” suffix.</p>
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<p>So let us start. Given that you are going to use Icarus Verilog as part of
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||
your design process, the first thing to do as a designer is learn how to
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compile and execute even the most trivial design. For the purposes of
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simulation, we use as our example the most trivial simulation, a simple Hello,
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||
World program.</p>
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<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="k">module</span><span class="w"> </span><span class="n">hello</span><span class="p">;</span>
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</span><span data-line="2"><span class="w"> </span><span class="k">initial</span>
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</span><span data-line="3"><span class="w"> </span><span class="k">begin</span>
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</span><span data-line="4"><span class="w"> </span><span class="nb">$display</span><span class="p">(</span><span class="s">"Hello, World"</span><span class="p">);</span>
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</span><span data-line="5"><span class="w"> </span><span class="nb">$finish</span><span class="w"> </span><span class="p">;</span>
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</span><span data-line="6"><span class="w"> </span><span class="k">end</span>
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</span><span data-line="7"><span class="k">endmodule</span>
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</span></pre></div>
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</div>
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<p>Use a text editor to place the program in a text file, hello.v, then compile
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this program with the command:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">% iverilog -o hello hello.v
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</span></pre></div>
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||
</div>
|
||
<p>The results of this compile are placed into the file “hello”, because the “-o”
|
||
flag tells the compiler where to place the compiled result. Next, execute the
|
||
compiled program like so:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">% vvp hello
|
||
</span><span data-line="2">Hello, World
|
||
</span></pre></div>
|
||
</div>
|
||
<p>And there it is, the program has been executed. So what happened? The first
|
||
step, the “iverilog” command, read and interpreted the source file, then
|
||
generated a compiled result. The compiled form may be selected by command line
|
||
switches, but the default is the “vvp” format, which is actually run later, as
|
||
needed. The “vvp” command of the second step interpreted the “hello” file from
|
||
the first step, causing the program to execute.</p>
|
||
<p>The “iverilog” and “vvp” commands are the most important commands available to
|
||
users of Icarus Verilog. The “iverilog” command is the compiler, and the “vvp”
|
||
command is the simulation runtime engine. What sort of output the compiler
|
||
actually creates is controlled by command line switches, but normally it
|
||
produces output in the default vvp format, which is in turn executed by the
|
||
vvp program.</p>
|
||
<p>As designs get larger and more complex, they gain hierarchy in the form of
|
||
modules that are instantiated within others, and it becomes convenient to
|
||
organize them into multiple files. A common convention is to write one
|
||
moderate sized module per file (or group related tiny modules into a single
|
||
file) then combine the files of the design together during compilation. For
|
||
example, the counter model in counter.v</p>
|
||
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="k">module</span><span class="w"> </span><span class="n">counter</span><span class="p">(</span><span class="n">out</span><span class="p">,</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">);</span>
|
||
</span><span data-line="2">
|
||
</span><span data-line="3"><span class="w"> </span><span class="k">parameter</span><span class="w"> </span><span class="n">WIDTH</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">8</span><span class="p">;</span>
|
||
</span><span data-line="4">
|
||
</span><span data-line="5"><span class="w"> </span><span class="k">output</span><span class="w"> </span><span class="p">[</span><span class="n">WIDTH</span><span class="o">-</span><span class="mh">1</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">out</span><span class="p">;</span>
|
||
</span><span data-line="6"><span class="w"> </span><span class="k">input</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">;</span>
|
||
</span><span data-line="7">
|
||
</span><span data-line="8"><span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="p">[</span><span class="n">WIDTH</span><span class="o">-</span><span class="mh">1</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">out</span><span class="p">;</span>
|
||
</span><span data-line="9"><span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">;</span>
|
||
</span><span data-line="10">
|
||
</span><span data-line="11"><span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">@(</span><span class="k">posedge</span><span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="k">or</span><span class="w"> </span><span class="k">posedge</span><span class="w"> </span><span class="n">reset</span><span class="p">)</span>
|
||
</span><span data-line="12"><span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">reset</span><span class="p">)</span>
|
||
</span><span data-line="13"><span class="w"> </span><span class="n">out</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="14"><span class="w"> </span><span class="k">else</span>
|
||
</span><span data-line="15"><span class="w"> </span><span class="n">out</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="n">out</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
||
</span><span data-line="16">
|
||
</span><span data-line="17"><span class="k">endmodule</span><span class="w"> </span><span class="c1">// counter</span>
|
||
</span></pre></div>
|
||
</div>
|
||
<p>and the test bench in counter_tb.v</p>
|
||
<div class="highlight-verilog notranslate"><div class="highlight"><pre><span></span><span data-line="1"><span class="k">module</span><span class="w"> </span><span class="n">test</span><span class="p">;</span>
|
||
</span><span data-line="2">
|
||
</span><span data-line="3"><span class="w"> </span><span class="cm">/* Make a reset that pulses once. */</span>
|
||
</span><span data-line="4"><span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="5"><span class="w"> </span><span class="k">initial</span><span class="w"> </span><span class="k">begin</span>
|
||
</span><span data-line="6"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">17</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
||
</span><span data-line="7"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">11</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="8"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">29</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">1</span><span class="p">;</span>
|
||
</span><span data-line="9"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">11</span><span class="w"> </span><span class="n">reset</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="10"><span class="w"> </span><span class="p">#</span><span class="w"> </span><span class="mh">100</span><span class="w"> </span><span class="nb">$stop</span><span class="p">;</span>
|
||
</span><span data-line="11"><span class="w"> </span><span class="k">end</span>
|
||
</span><span data-line="12">
|
||
</span><span data-line="13"><span class="w"> </span><span class="cm">/* Make a regular pulsing clock. */</span>
|
||
</span><span data-line="14"><span class="w"> </span><span class="kt">reg</span><span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mh">0</span><span class="p">;</span>
|
||
</span><span data-line="15"><span class="w"> </span><span class="k">always</span><span class="w"> </span><span class="p">#</span><span class="mh">5</span><span class="w"> </span><span class="n">clk</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="o">!</span><span class="n">clk</span><span class="p">;</span>
|
||
</span><span data-line="16">
|
||
</span><span data-line="17"><span class="w"> </span><span class="kt">wire</span><span class="w"> </span><span class="p">[</span><span class="mh">7</span><span class="o">:</span><span class="mh">0</span><span class="p">]</span><span class="w"> </span><span class="n">value</span><span class="p">;</span>
|
||
</span><span data-line="18"><span class="w"> </span><span class="n">counter</span><span class="w"> </span><span class="n">c1</span><span class="w"> </span><span class="p">(</span><span class="n">value</span><span class="p">,</span><span class="w"> </span><span class="n">clk</span><span class="p">,</span><span class="w"> </span><span class="n">reset</span><span class="p">);</span>
|
||
</span><span data-line="19">
|
||
</span><span data-line="20"><span class="w"> </span><span class="k">initial</span>
|
||
</span><span data-line="21"><span class="w"> </span><span class="nb">$monitor</span><span class="p">(</span><span class="s">"At time %t, value = %h (%0d)"</span><span class="p">,</span>
|
||
</span><span data-line="22"><span class="w"> </span><span class="nb">$time</span><span class="p">,</span><span class="w"> </span><span class="n">value</span><span class="p">,</span><span class="w"> </span><span class="n">value</span><span class="p">);</span>
|
||
</span><span data-line="23"><span class="k">endmodule</span><span class="w"> </span><span class="c1">// test</span>
|
||
</span></pre></div>
|
||
</div>
|
||
<p>are written into different files.</p>
|
||
<p>The “iverilog” command supports multi-file designs by two methods. The
|
||
simplest is to list the files on the command line:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">% iverilog -o my_design counter_tb.v counter.v
|
||
</span><span data-line="2">% vvp my_design
|
||
</span></pre></div>
|
||
</div>
|
||
<p>This command compiles the design, which is spread across two input files, and
|
||
generates the compiled result into the “my_design” file. This works for small
|
||
to medium sized designs, but gets cumbersome when there are lots of files.</p>
|
||
<p>Another technique is to use a commandfile, which lists the input files in a
|
||
text file. For example, create a text file called “file_list.txt” with the
|
||
files listed one per line:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">counter.v
|
||
</span><span data-line="2">counter_tb.v
|
||
</span></pre></div>
|
||
</div>
|
||
<p>Then compile and execute the design with a command like so:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">% iverilog -o my_design -c file_list.txt
|
||
</span><span data-line="2">% vvp my_design
|
||
</span></pre></div>
|
||
</div>
|
||
<p>The command file technique clearly supports much larger designs simply by
|
||
saving you the trouble of listing all the source files on the command
|
||
line. Name the files that are part of the design in the command file and use
|
||
the “-c” flag to tell iverilog to read the command file as a list of Verilog
|
||
input files.</p>
|
||
<p>As designs get more complicated, they almost certainly contain many Verilog
|
||
modules that represent the hierarchy of your design. Typically, there is one
|
||
module that instantiates other modules but is not instantiated by any other
|
||
modules. This is called a root module. Icarus Verilog chooses as roots (There
|
||
can be more than one root) all the modules that are not instantiated by other
|
||
modules. If there are no such modules, the compiler will not be able to choose
|
||
any root, and the designer must use the “-sroot” switch to identify the root
|
||
module, like this:</p>
|
||
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span><span data-line="1">% iverilog -s main -o hello hello.v
|
||
</span></pre></div>
|
||
</div>
|
||
<p>If there are multiple candidate roots, all of them will be elaborated. The
|
||
compiler will do this even if there are many root modules that you do not
|
||
intend to simulate, or that have no effect on the simulation. This can happen,
|
||
for example, if you include a source file that has multiple modules, but are
|
||
only really interested in some of them. The “-s” flag identifies a specific
|
||
root module and also turns off the automatic search for other root
|
||
modules. You can use this feature to prevent instantiation of unwanted roots.</p>
|
||
<p>As designs get even larger, they become spread across many dozens or even
|
||
hundreds of files. When designs are that complex, more advanced source code
|
||
management techniques become necessary. These are described in later chapters,
|
||
along with other advanced design management techniques supported by Icarus
|
||
Verilog.</p>
|
||
</section>
|
||
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