99 lines
3.6 KiB
ReStructuredText
99 lines
3.6 KiB
ReStructuredText
🎉 Release V13.0
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================
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The Icarus Verilog development team is pleased to announce **Release V13** of Icarus Verilog.
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Release V13 builds on the V12 series with a focus on correctness, runtime stability, improved
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diagnostics, and incremental standard conformance improvements.
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----
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🐞 Bug Fix Summary
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------------------
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Release V13 resolves numerous issues reported against V12, including:
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* Incorrect signed constant handling.
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* Generate block naming collisions.
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* Elaboration-time assertion failures.
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* Runtime crashes in malformed corner cases.
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* Memory management issues during elaboration and simulation.
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----
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🔄 Major Changes in V13
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=======================
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🧠 Language & Elaboration Fixes
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-------------------------------
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Release V13 includes multiple fixes to elaboration and expression handling:
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* Resolved generate block scope resolution issues affecting nested and conditional generate constructs.
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* Corrected signed arithmetic corner cases, including shift and width propagation behavior.
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* Fixed constant expression evaluation inconsistencies during parameter elaboration.
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* Improved handling of packed and unpacked arrays in assignments and port binding corner cases.
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* Addressed elaboration-time assertion failures triggered by malformed or ambiguous constructs.
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* Corrected several source-location reporting issues for elaboration errors.
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These changes improve standards conformance and eliminate behavioral inconsistencies observed in the V12 series.
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----
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⚙️ Simulator (vvp) Improvements
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-------------------------------
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The `vvp` runtime engine has received internal stability and correctness updates:
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* Improved event scheduling behavior in zero-delay and non-blocking assignment scenarios.
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* Fixed race-condition corner cases uncovered by expanded regression testing.
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* Eliminated memory leaks affecting long-running or large simulations.
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* Resolved crash conditions caused by invalid internal state transitions.
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* Improved robustness of `$dumpvars` handling in large hierarchical designs.
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* General runtime consistency and determinism improvements.
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`vvp` continues to enforce version matching between the runtime and generated bytecode. Designs
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must be recompiled after upgrading.
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----
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🔌 VPI Updates
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--------------
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Fixes improve VPI reliability and conformance:
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* Corrected hierarchical object lookup behavior in specific corner cases.
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* Improved stability of callback registration during startup and shutdown.
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* Fixed invalid handle dereference scenarios that could result in segmentation faults.
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* Addressed inconsistencies in VPI object property reporting.
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----
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🛠 Diagnostics & Toolchain
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--------------------------
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* Improved clarity and consistency of error and warning messages.
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* Better reporting of width mismatches and implicit net declarations.
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* More accurate diagnostic source locations.
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* Build system updates for compatibility with modern compiler toolchains.
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* Regression suite expansion and CI validation improvements.
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----
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📦 Upgrade Notes
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----------------
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* Recompile all designs when upgrading from V12 or any other prior version.
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* Review warnings carefully; improved diagnostics may expose previously silent issues.
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* The only known breaking change is that wires must now be declared before use; which is required in the standard (see `gh1287 <https://github.com/steveicarus/iverilog/issues/1287>`__).
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----
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🙏 Acknowledgments
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------------------
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We thank all contributors who reported issues, submitted patches, expanded regression coverage, and
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improved documentation. Release 13 reflects continued community effort toward improving correctness,
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stability, and maintainability.
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