131 lines
3.8 KiB
C++
131 lines
3.8 KiB
C++
#ifndef __PUdp_H
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#define __PUdp_H
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/*
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* Copyright (c) 1998-2004 Stephen Williams (steve@picturel.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: PUdp.h,v 1.12 2004/03/08 00:47:44 steve Exp $"
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#endif
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# include <map>
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# include "StringHeap.h"
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# include "svector.h"
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# include "verinum.h"
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class PExpr;
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/*
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* This class represents a parsed UDP. This is a much simpler object
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* then a module or macromodule.
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*
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* - all ports are scalar,
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* - pin 0 (the first port) is always output,
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* and the remaining pins are input.
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*
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* Thus, the ports can be represented as an ordered list of pin names.
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* If the output port is declared as a register in the Verilog source,
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* then this is a sequential UDP and the sequential flag is set to true.
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*
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* STATE TABLE
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* Each entry in the state table is given as a string with the same
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* number of characters as inputs. If the UDP is sequential, a
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* character is also included at the end of the string to represent
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* the current output.
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*
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* If the UDP is sequential, the "initial" member is taken to be the
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* initial value assigned in the source, or 'x' if none is given.
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*/
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class PUdp {
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public:
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explicit PUdp(perm_string n, unsigned nports);
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svector<string>ports;
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unsigned find_port(const char*name);
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bool sequential;
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svector<string>tinput;
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svector<char> tcurrent;
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svector<char> toutput;
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verinum::V initial;
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map<string,PExpr*> attributes;
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void dump(ostream&out) const;
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perm_string name_;
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private:
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private: // Not implemented
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PUdp(const PUdp&);
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PUdp& operator= (const PUdp&);
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};
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/*
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* $Log: PUdp.h,v $
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* Revision 1.12 2004/03/08 00:47:44 steve
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* primitive ports can bind bi name.
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*
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* Revision 1.11 2004/02/18 17:11:54 steve
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* Use perm_strings for named langiage items.
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*
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* Revision 1.10 2003/07/15 05:07:13 steve
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* Move PUdp constructor into compiled file.
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*
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* Revision 1.9 2003/07/15 03:49:22 steve
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* Spelling fixes.
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*
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* Revision 1.8 2003/01/30 16:23:07 steve
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* Spelling fixes.
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*
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* Revision 1.7 2002/08/12 01:34:58 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.6 2002/05/23 03:08:51 steve
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* Add language support for Verilog-2001 attribute
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* syntax. Hook this support into existing $attribute
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* handling, and add number and void value types.
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*
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* Add to the ivl_target API new functions for access
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* of complex attributes attached to gates.
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*
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* Revision 1.5 2001/04/22 23:09:45 steve
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* More UDP consolidation from Stephan Boettcher.
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*
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* Revision 1.4 2000/02/23 02:56:53 steve
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* Macintosh compilers do not support ident.
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*
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* Revision 1.3 1999/06/15 03:44:53 steve
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* Get rid of the STL vector template.
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*
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* Revision 1.2 1998/12/01 00:42:13 steve
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* Elaborate UDP devices,
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* Support UDP type attributes, and
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* pass those attributes to nodes that
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* are instantiated by elaboration,
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* Put modules into a map instead of
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* a simple list.
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*
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* Revision 1.1 1998/11/25 02:35:53 steve
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* Parse UDP primitives all the way to pform.
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*
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*/
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#endif
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