274 lines
7.1 KiB
C++
274 lines
7.1 KiB
C++
#ifndef __logic_H
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#define __logic_H
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/*
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* Copyright (c) 2000-2005 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: logic.h,v 1.25 2006/11/28 05:57:20 steve Exp $"
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#endif
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# include "vvp_net.h"
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# include "schedule.h"
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# include <stddef.h>
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/*
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* Table driven functor. This kind of node takes 4 inputs and
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* generates a single output. The logic is bitwise, and implemented
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* with a lookup table.
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*/
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class table_functor_s: public vvp_net_fun_t {
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public:
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typedef const unsigned char *truth_t;
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explicit table_functor_s(truth_t t);
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virtual ~table_functor_s();
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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private:
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truth_t table;
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vvp_vector4_t input_[4];
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};
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/*
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* vvp_fun_boolean_ is just a common hook for holding operands.
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*/
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class vvp_fun_boolean_ : public vvp_net_fun_t, protected vvp_gen_event_s {
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public:
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explicit vvp_fun_boolean_(unsigned wid);
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~vvp_fun_boolean_();
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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protected:
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vvp_vector4_t input_[4];
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vvp_net_t*net_;
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};
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class vvp_fun_and : public vvp_fun_boolean_ {
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public:
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explicit vvp_fun_and(unsigned wid, bool invert);
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~vvp_fun_and();
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private:
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void run_run();
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bool invert_;
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};
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class vvp_fun_eeq : public vvp_fun_boolean_ {
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public:
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explicit vvp_fun_eeq(unsigned wid, bool invert);
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~vvp_fun_eeq();
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private:
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void run_run();
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bool invert_;
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};
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/*
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* The buffer functor is a very primitive functor that takes the input
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* from port-0 (and only port-0) and retransmits it as a vvp_vector4_t.
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* The retransmitted vector has all Z values changed to X, just like
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* the buf(Q,D) gate in Verilog.
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*/
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class vvp_fun_buf: public vvp_net_fun_t, private vvp_gen_event_s {
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public:
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explicit vvp_fun_buf();
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virtual ~vvp_fun_buf();
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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private:
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void run_run();
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private:
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vvp_vector4_t input_;
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vvp_net_t*net_;
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};
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/*
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* The vvp_fun_bufz is like the vvp_fun_buf, but it does not change
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* Z values to X -- it passes Z values unchanged.
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*/
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class vvp_fun_bufz: public vvp_net_fun_t {
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public:
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explicit vvp_fun_bufz();
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virtual ~vvp_fun_bufz();
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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void recv_real(vvp_net_ptr_t p, double bit);
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private:
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};
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/*
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* The muxz functor is an A-B mux device, with the data inputs on
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* ports 0 and 1. port 2 is the select input.
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*
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* The select input must be 1 bit wide. If it is 0, then the port-0
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* vector is passed out. If select is 1, then port-1 is passed
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* out. Otherwise, a vector is passed out that reflects x?: behavior
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* in verilog. The width of the blended output is the width of the largest
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* input (port-0 or port-1) to enter the device. The narrow vector is
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* padded with X values.
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*/
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class vvp_fun_muxz : public vvp_net_fun_t {
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public:
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explicit vvp_fun_muxz(unsigned width);
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virtual ~vvp_fun_muxz();
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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private:
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vvp_vector4_t a_;
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vvp_vector4_t b_;
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int select_;
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};
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class vvp_fun_muxr : public vvp_net_fun_t {
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public:
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explicit vvp_fun_muxr();
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virtual ~vvp_fun_muxr();
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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void recv_real(vvp_net_ptr_t p, double bit);
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private:
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double a_;
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double b_;
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int select_;
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};
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class vvp_fun_not: public vvp_net_fun_t, private vvp_gen_event_s {
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public:
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explicit vvp_fun_not();
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virtual ~vvp_fun_not();
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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private:
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void run_run();
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private:
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vvp_vector4_t input_;
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vvp_net_t*net_;
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};
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class vvp_fun_or : public vvp_fun_boolean_ {
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public:
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explicit vvp_fun_or(unsigned wid, bool invert);
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~vvp_fun_or();
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private:
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void run_run();
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bool invert_;
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};
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class vvp_fun_xor : public vvp_fun_boolean_ {
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public:
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explicit vvp_fun_xor(unsigned wid, bool invert);
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~vvp_fun_xor();
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private:
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void run_run();
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bool invert_;
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};
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// table functor types
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extern const unsigned char ft_MUXX[];
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extern const unsigned char ft_EEQ[];
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extern const unsigned char ft_TRIAND[];
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extern const unsigned char ft_TRIOR[];
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/*
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* $Log: logic.h,v $
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* Revision 1.25 2006/11/28 05:57:20 steve
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* Use new vvp_fun_XXX in place of old functor table for NAND/NOR/XNOR/EEQ.
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*
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* Revision 1.24 2005/09/19 21:45:09 steve
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* Use lazy eval of BUF/NOT/OR/XOR gates.
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*
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* Revision 1.23 2005/09/01 04:08:47 steve
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* Support MUXR functors.
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*
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* Revision 1.22 2005/07/06 04:29:25 steve
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* Implement real valued signals and arith nodes.
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*
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* Revision 1.21 2005/06/26 21:08:38 steve
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* AND functor explicitly knows its width.
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*
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* Revision 1.20 2005/06/26 18:06:30 steve
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* AND gates propogate through scheduler, not directly.
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*
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* Revision 1.19 2005/06/22 00:04:49 steve
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* Reduce vvp_vector4 copies by using const references.
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*
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* Revision 1.18 2005/06/17 03:46:53 steve
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* Make functors know their own width.
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*
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* Revision 1.17 2005/06/12 21:56:16 steve
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* Remove unused ft_MOS truth tables.
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*
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* Revision 1.16 2005/05/14 19:43:23 steve
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* Move functor delays to vvp_delay_fun object.
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*
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* Revision 1.15 2005/05/13 05:13:12 steve
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* Give buffers support for simple delays.
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*
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* Revision 1.14 2005/04/13 06:34:20 steve
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* Add vvp driver functor for logic outputs,
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* Add ostream output operators for debugging.
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*
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* Revision 1.13 2005/02/12 23:05:25 steve
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* Cleanup unused truth tables.
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*
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* Revision 1.11 2005/01/29 17:52:06 steve
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* move AND to buitin instead of table.
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*
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* Revision 1.10 2004/12/31 05:56:36 steve
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* Add specific BUFZ functor.
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*
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* Revision 1.9 2004/12/29 23:45:13 steve
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* Add the part concatenation node (.concat).
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*
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* Add a vvp_event_anyedge class to handle the special
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* case of .event statements of edge type. This also
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* frees the posedge/negedge types to handle all 4 inputs.
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*
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* Implement table functor recv_vec4 method to receive
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* and process vectors.
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*
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* Revision 1.8 2004/12/11 02:31:29 steve
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* Rework of internals to carry vectors through nexus instead
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* of single bits. Make the ivl, tgt-vvp and vvp initial changes
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* down this path.
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*
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*/
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#endif // __logic_H
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