712 lines
16 KiB
C++
712 lines
16 KiB
C++
/*
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* Copyright (c) 2001-2004 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: logic.cc,v 1.38 2007/02/12 05:08:27 steve Exp $"
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#endif
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# include "logic.h"
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# include "compile.h"
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# include "bufif.h"
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# include "npmos.h"
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# include "schedule.h"
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# include "delay.h"
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# include "statistics.h"
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# include <string.h>
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# include <assert.h>
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# include <stdlib.h>
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#ifdef HAVE_MALLOC_H
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# include <malloc.h>
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#endif
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/*
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* Implementation of the table functor, which provides logic with up
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* to 4 inputs.
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*/
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table_functor_s::table_functor_s(truth_t t)
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: table(t)
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{
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count_functors_table += 1;
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}
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table_functor_s::~table_functor_s()
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{
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}
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/*
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* WARNING: This function assumes that the table generator encodes the
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* values 0/1/x/z the same as the vvp_bit4_t enumeration values.
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*/
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void table_functor_s::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&val)
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{
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input_[ptr.port()] = val;
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vvp_vector4_t result (val.size());
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for (unsigned idx = 0 ; idx < val.size() ; idx += 1) {
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unsigned lookup = 0;
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for (unsigned pdx = 4 ; pdx > 0 ; pdx -= 1) {
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lookup <<= 2;
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if (idx < input_[pdx-1].size())
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lookup |= input_[pdx-1].value(idx);
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}
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unsigned off = lookup / 4;
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unsigned shift = lookup % 4 * 2;
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unsigned bit_val = table[off] >> shift;
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bit_val &= 3;
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result.set_bit(idx, (vvp_bit4_t)bit_val);
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}
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vvp_send_vec4(ptr.ptr()->out, result);
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}
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vvp_fun_boolean_::vvp_fun_boolean_(unsigned wid)
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{
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net_ = 0;
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for (unsigned idx = 0 ; idx < 4 ; idx += 1)
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input_[idx] = vvp_vector4_t(wid);
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}
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vvp_fun_boolean_::~vvp_fun_boolean_()
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{
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}
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void vvp_fun_boolean_::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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unsigned port = ptr.port();
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if (input_[port] .eeq( bit ))
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return;
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input_[ptr.port()] = bit;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_generic(this, 0, false);
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}
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}
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vvp_fun_and::vvp_fun_and(unsigned wid, bool invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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{
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}
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vvp_fun_and::~vvp_fun_and()
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{
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}
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void vvp_fun_and::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_[0]);
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for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
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vvp_bit4_t bitbit = result.value(idx);
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for (unsigned pdx = 1 ; pdx < 4 ; pdx += 1) {
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if (input_[pdx].size() < idx) {
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bitbit = BIT4_X;
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break;
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}
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bitbit = bitbit & input_[pdx].value(idx);
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}
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if (invert_)
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bitbit = ~bitbit;
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result.set_bit(idx, bitbit);
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}
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vvp_send_vec4(ptr->out, result);
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}
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vvp_fun_eeq::vvp_fun_eeq(unsigned wid, bool invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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{
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}
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vvp_fun_eeq::~vvp_fun_eeq()
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{
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}
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void vvp_fun_eeq::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_[0]);
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for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
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vvp_bit4_t bitbit = result.value(idx);
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bitbit = (bitbit == input_[1].value(idx))? BIT4_1 : BIT4_0;
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if (invert_)
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bitbit = ~bitbit;
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result.set_bit(idx, bitbit);
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}
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vvp_send_vec4(ptr->out, result);
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}
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vvp_fun_buf::vvp_fun_buf()
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{
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net_ = 0;
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count_functors_table += 1;
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}
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vvp_fun_buf::~vvp_fun_buf()
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{
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}
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/*
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* The buf functor is very simple--change the z bits to x bits in the
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* vector it passes, and propagate the result.
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*/
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void vvp_fun_buf::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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if (ptr.port() != 0)
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return;
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if (input_ .eeq( bit ))
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return;
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input_ = bit;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_generic(this, 0, false);
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}
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}
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void vvp_fun_buf::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t tmp (input_);
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tmp.change_z2x();
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vvp_send_vec4(ptr->out, tmp);
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}
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vvp_fun_bufz::vvp_fun_bufz()
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{
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count_functors_table += 1;
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}
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vvp_fun_bufz::~vvp_fun_bufz()
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{
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}
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/*
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* The bufz is similar to the buf device, except that it does not
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* bother translating z bits to x.
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*/
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void vvp_fun_bufz::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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if (ptr.port() != 0)
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return;
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vvp_send_vec4(ptr.ptr()->out, bit);
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}
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void vvp_fun_bufz::recv_real(vvp_net_ptr_t ptr, double bit)
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{
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if (ptr.port() != 0)
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return;
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vvp_send_real(ptr.ptr()->out, bit);
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}
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vvp_fun_muxr::vvp_fun_muxr()
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: a_(0.0), b_(0.0)
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{
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count_functors_table += 1;
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select_ = 2;
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}
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vvp_fun_muxr::~vvp_fun_muxr()
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{
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}
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void vvp_fun_muxr::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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/* The real valued mux can only take in the select as a
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vector4_t. the muxed data is rea. */
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if (ptr.port() != 2)
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return;
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assert(bit.size() == 1);
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switch (bit.value(0)) {
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case BIT4_0:
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select_ = 0;
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break;
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case BIT4_1:
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select_ = 1;
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break;
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default:
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select_ = 2;
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}
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switch (select_) {
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case 0:
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vvp_send_real(ptr.ptr()->out, a_);
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break;
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case 1:
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vvp_send_real(ptr.ptr()->out, b_);
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break;
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default:
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if (a_ == b_) {
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vvp_send_real(ptr.ptr()->out, a_);
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} else {
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// Should send NaN?
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vvp_send_real(ptr.ptr()->out, 0.0);
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}
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break;
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}
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}
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void vvp_fun_muxr::recv_real(vvp_net_ptr_t ptr, double bit)
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{
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switch (ptr.port()) {
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case 0:
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if (a_ == bit)
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break;
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a_ = bit;
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if (select_ == 0)
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vvp_send_real(ptr.ptr()->out, a_);
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break;
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case 1:
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if (b_ == bit)
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break;
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b_ = bit;
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if (select_ == 1)
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vvp_send_real(ptr.ptr()->out, b_);
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break;
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default:
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assert(0);
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}
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}
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vvp_fun_muxz::vvp_fun_muxz(unsigned wid)
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: a_(wid), b_(wid)
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{
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count_functors_table += 1;
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select_ = 2;
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for (unsigned idx = 0 ; idx < wid ; idx += 1) {
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a_.set_bit(idx, BIT4_X);
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b_.set_bit(idx, BIT4_X);
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}
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}
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vvp_fun_muxz::~vvp_fun_muxz()
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{
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}
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void vvp_fun_muxz::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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switch (ptr.port()) {
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case 0:
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a_ = bit;
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break;
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case 1:
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b_ = bit;
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break;
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case 2:
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assert(bit.size() == 1);
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switch (bit.value(0)) {
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case BIT4_0:
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select_ = 0;
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break;
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case BIT4_1:
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select_ = 1;
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break;
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default:
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select_ = 2;
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}
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break;
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default:
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return;
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}
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switch (select_) {
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case 0:
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vvp_send_vec4(ptr.ptr()->out, a_);
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break;
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case 1:
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vvp_send_vec4(ptr.ptr()->out, b_);
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break;
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default:
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{
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unsigned min_size = a_.size();
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unsigned max_size = a_.size();
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if (b_.size() < min_size)
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min_size = b_.size();
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if (b_.size() > max_size)
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max_size = b_.size();
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vvp_vector4_t res (max_size);
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for (unsigned idx = 0 ; idx < min_size ; idx += 1) {
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if (a_.value(idx) == b_.value(idx))
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res.set_bit(idx, a_.value(idx));
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else
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res.set_bit(idx, BIT4_X);
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}
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for (unsigned idx = min_size ; idx < max_size ; idx += 1)
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res.set_bit(idx, BIT4_X);
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vvp_send_vec4(ptr.ptr()->out, res);
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}
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break;
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}
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}
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vvp_fun_not::vvp_fun_not()
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{
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net_ = 0;
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count_functors_table += 1;
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}
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vvp_fun_not::~vvp_fun_not()
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{
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}
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/*
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* The buf functor is very simple--change the z bits to x bits in the
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* vector it passes, and propagate the result.
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*/
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void vvp_fun_not::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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{
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if (ptr.port() != 0)
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return;
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if (input_ .eeq( bit ))
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return;
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input_ = bit;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_generic(this, 0, false);
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}
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}
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void vvp_fun_not::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_);
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for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
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vvp_bit4_t bitbit = ~ result.value(idx);
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result.set_bit(idx, bitbit);
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}
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vvp_send_vec4(ptr->out, result);
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}
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vvp_fun_or::vvp_fun_or(unsigned wid, bool invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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{
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}
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vvp_fun_or::~vvp_fun_or()
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{
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}
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void vvp_fun_or::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_[0]);
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for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
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vvp_bit4_t bitbit = result.value(idx);
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for (unsigned pdx = 1 ; pdx < 4 ; pdx += 1) {
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if (input_[pdx].size() < idx) {
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bitbit = BIT4_X;
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break;
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}
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bitbit = bitbit | input_[pdx].value(idx);
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}
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if (invert_)
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bitbit = ~bitbit;
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result.set_bit(idx, bitbit);
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}
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vvp_send_vec4(ptr->out, result);
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}
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vvp_fun_xor::vvp_fun_xor(unsigned wid, bool invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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{
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}
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vvp_fun_xor::~vvp_fun_xor()
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{
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}
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void vvp_fun_xor::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_[0]);
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for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
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vvp_bit4_t bitbit = result.value(idx);
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for (unsigned pdx = 1 ; pdx < 4 ; pdx += 1) {
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if (input_[pdx].size() < idx) {
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bitbit = BIT4_X;
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break;
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}
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bitbit = bitbit ^ input_[pdx].value(idx);
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}
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if (invert_)
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bitbit = ~bitbit;
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result.set_bit(idx, bitbit);
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}
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vvp_send_vec4(ptr->out, result);
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}
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/*
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* The parser calls this function to create a logic functor. I allocate a
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* functor, and map the name to the vvp_ipoint_t address for the
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* functor. Also resolve the inputs to the functor.
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*/
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void compile_functor(char*label, char*type, unsigned width,
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unsigned ostr0, unsigned ostr1,
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unsigned argc, struct symb_s*argv)
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{
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vvp_net_fun_t* obj = 0;
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bool strength_aware = false;
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if (strcmp(type, "OR") == 0) {
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obj = new vvp_fun_or(width, false);
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} else if (strcmp(type, "AND") == 0) {
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obj = new vvp_fun_and(width, false);
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} else if (strcmp(type, "BUF") == 0) {
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obj = new vvp_fun_buf();
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} else if (strcmp(type, "BUFIF0") == 0) {
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obj = new vvp_fun_bufif(true,false, ostr0, ostr1);
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strength_aware = true;
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} else if (strcmp(type, "BUFIF1") == 0) {
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obj = new vvp_fun_bufif(false,false, ostr0, ostr1);
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strength_aware = true;
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} else if (strcmp(type, "NAND") == 0) {
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obj = new vvp_fun_and(width, true);
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} else if (strcmp(type, "NOR") == 0) {
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obj = new vvp_fun_or(width, true);
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} else if (strcmp(type, "NOTIF0") == 0) {
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obj = new vvp_fun_bufif(true,true, ostr0, ostr1);
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strength_aware = true;
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} else if (strcmp(type, "NOTIF1") == 0) {
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obj = new vvp_fun_bufif(false,true, ostr0, ostr1);
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strength_aware = true;
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} else if (strcmp(type, "BUFZ") == 0) {
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obj = new vvp_fun_bufz();
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} else if (strcmp(type, "MUXR") == 0) {
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obj = new vvp_fun_muxr;
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} else if (strcmp(type, "MUXX") == 0) {
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obj = new table_functor_s(ft_MUXX);
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} else if (strcmp(type, "MUXZ") == 0) {
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obj = new vvp_fun_muxz(width);
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} else if (strcmp(type, "NMOS") == 0) {
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obj = new vvp_fun_pmos(true);
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} else if (strcmp(type, "PMOS") == 0) {
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obj = new vvp_fun_pmos(false);
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} else if (strcmp(type, "RNMOS") == 0) {
|
|
obj = new vvp_fun_rpmos(true);
|
|
|
|
} else if (strcmp(type, "RPMOS") == 0) {
|
|
obj = new vvp_fun_rpmos(false);
|
|
|
|
} else if (strcmp(type, "EEQ") == 0) {
|
|
obj = new vvp_fun_eeq(width, false);
|
|
|
|
} else if (strcmp(type, "NOT") == 0) {
|
|
obj = new vvp_fun_not();
|
|
|
|
} else if (strcmp(type, "XNOR") == 0) {
|
|
obj = new vvp_fun_xor(width, true);
|
|
|
|
} else if (strcmp(type, "XOR") == 0) {
|
|
obj = new vvp_fun_xor(width, false);
|
|
|
|
} else {
|
|
yyerror("invalid functor type.");
|
|
free(type);
|
|
free(argv);
|
|
free(label);
|
|
return;
|
|
}
|
|
|
|
free(type);
|
|
|
|
assert(argc <= 4);
|
|
vvp_net_t*net = new vvp_net_t;
|
|
net->fun = obj;
|
|
|
|
inputs_connect(net, argc, argv);
|
|
free(argv);
|
|
|
|
/* If both the strengths are the default strong drive, then
|
|
there is no need for a specialized driver. Attach the label
|
|
to this node and we are finished. */
|
|
if (strength_aware || ostr0 == 6 && ostr1 == 6) {
|
|
define_functor_symbol(label, net);
|
|
free(label);
|
|
return;
|
|
}
|
|
|
|
vvp_net_t*net_drv = new vvp_net_t;
|
|
vvp_net_fun_t*obj_drv = new vvp_fun_drive(BIT4_X, ostr0, ostr1);
|
|
net_drv->fun = obj_drv;
|
|
|
|
/* Point the gate to the drive node. */
|
|
net->out = vvp_net_ptr_t(net_drv, 0);
|
|
|
|
define_functor_symbol(label, net_drv);
|
|
free(label);
|
|
}
|
|
|
|
|
|
/*
|
|
* $Log: logic.cc,v $
|
|
* Revision 1.38 2007/02/12 05:08:27 steve
|
|
* NAND output is inverted once AFTER AND is calculated.
|
|
*
|
|
* Revision 1.37 2006/11/28 05:57:20 steve
|
|
* Use new vvp_fun_XXX in place of old functor table for NAND/NOR/XNOR/EEQ.
|
|
*
|
|
* Revision 1.36 2006/01/02 05:32:07 steve
|
|
* Require explicit delay node from source.
|
|
*
|
|
* Revision 1.35 2005/09/19 22:47:28 steve
|
|
* Prevent some excess scheduling of logic propagation events.
|
|
*
|
|
* Revision 1.34 2005/09/19 21:45:09 steve
|
|
* Use lazy eval of BUF/NOT/OR/XOR gates.
|
|
*
|
|
* Revision 1.33 2005/09/01 04:08:47 steve
|
|
* Support MUXR functors.
|
|
*
|
|
* Revision 1.32 2005/07/06 04:29:25 steve
|
|
* Implement real valued signals and arith nodes.
|
|
*
|
|
* Revision 1.31 2005/06/26 21:08:38 steve
|
|
* AND functor explicitly knows its width.
|
|
*
|
|
* Revision 1.30 2005/06/26 18:06:29 steve
|
|
* AND gates propogate through scheduler, not directly.
|
|
*
|
|
* Revision 1.29 2005/06/22 00:04:49 steve
|
|
* Reduce vvp_vector4 copies by using const references.
|
|
*
|
|
* Revision 1.28 2005/06/21 22:48:23 steve
|
|
* Optimize vvp_scalar_t handling, and fun_buf Z handling.
|
|
*
|
|
* Revision 1.27 2005/06/17 03:46:52 steve
|
|
* Make functors know their own width.
|
|
*
|
|
* Revision 1.26 2005/06/12 15:13:37 steve
|
|
* Support resistive mos devices.
|
|
*
|
|
* Revision 1.25 2005/06/12 00:44:49 steve
|
|
* Implement nmos and pmos devices.
|
|
*
|
|
* Revision 1.24 2005/06/02 16:02:11 steve
|
|
* Add support for notif0/1 gates.
|
|
* Make delay nodes support inertial delay.
|
|
* Add the %force/link instruction.
|
|
*
|
|
* Revision 1.23 2005/05/14 19:43:23 steve
|
|
* Move functor delays to vvp_delay_fun object.
|
|
*
|
|
* Revision 1.22 2005/05/13 05:13:12 steve
|
|
* Give buffers support for simple delays.
|
|
*
|
|
* Revision 1.21 2005/04/13 06:34:20 steve
|
|
* Add vvp driver functor for logic outputs,
|
|
* Add ostream output operators for debugging.
|
|
*
|
|
* Revision 1.20 2005/04/03 05:45:51 steve
|
|
* Rework the vvp_delay_t class.
|
|
*
|
|
* Revision 1.19 2005/02/12 22:50:52 steve
|
|
* Implement the vvp_fun_muxz functor.
|
|
*
|
|
* Revision 1.18 2005/02/07 22:42:42 steve
|
|
* Add .repeat functor and BIFIF functors.
|
|
*
|
|
* Revision 1.17 2005/01/29 17:52:06 steve
|
|
* move AND to buitin instead of table.
|
|
*
|
|
* Revision 1.16 2004/12/31 05:56:36 steve
|
|
* Add specific BUFZ functor.
|
|
*
|
|
* Revision 1.15 2004/12/29 23:45:13 steve
|
|
* Add the part concatenation node (.concat).
|
|
*
|
|
* Add a vvp_event_anyedge class to handle the special
|
|
* case of .event statements of edge type. This also
|
|
* frees the posedge/negedge types to handle all 4 inputs.
|
|
*
|
|
* Implement table functor recv_vec4 method to receive
|
|
* and process vectors.
|
|
*
|
|
* Revision 1.14 2004/12/11 02:31:29 steve
|
|
* Rework of internals to carry vectors through nexus instead
|
|
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
|
|
* down this path.
|
|
*
|
|
*/
|
|
|