rpm spec file aware of stable versions.

parse.y has been updated to allow declarations outside a module (legal
in SystemVerilog), but not all types of declaration are supported yet.
Output a sorry or error message as appropriate.

driver-vpi/Makefile.in

@@ -86,7 +86,7 @@ config.h: $(srcdir)/config.h.in Makefile
 
 # Windows specific...
 res.rc: $(srcdir)/res.rc.in ../version.exe
-	sed -e 's;@PRODUCTVERSION@;'`../version.exe '%M,%m,%n,0'`';' \
+	sed -e 's;@PRODUCTVERSION@;'`../version.exe '%M,%n,0,0'`';' \
 	$(srcdir)/res.rc.in > $@
 
 res.o: res.rc

driver/iverilog.man.in

@@ -1,4 +1,4 @@
-.TH iverilog 1 "Aug 7th, 2015" "" "Version %M.%m.%n %E"
+.TH iverilog 1 "Aug 7th, 2015" "" "Version %M.%n%E"
 .SH NAME
 iverilog - Icarus Verilog compiler
 
@@ -30,7 +30,7 @@ different set of programs. The path given is used to locate
 \fIivlpp\fP, \fIivl\fP, code generators and the VPI modules.
 .TP 8
 .B -c\fIfile\fP -f\fIfile\fP
-These flags specifies an input file that contains a list of Verilog
+These flags specify an input file that contains a list of Verilog
 source files. This is similar to the \fIcommand file\fP of other
 Verilog simulators, in that it is a file that contains the file names
 instead of taking them on the command line. See \fBCommand Files\fP below.

driver/main.c

@@ -1047,19 +1047,10 @@ int main(int argc, char **argv)
 
       if (version_flag || verbose_flag) {
 	    printf("Icarus Verilog version " VERSION " (" VERSION_TAG ")\n\n");
-	    printf("Copyright 1998-2013 Stephen Williams\n\n");
+	    printf("Copyright 1998-2015 Stephen Williams\n\n");
 	    puts(NOTICE);
       }
 
-      if (synth_flag) {
-	    fprintf(stderr, "Warning: Synthesis is not currently being "
-	                    "maintained and may not\n");
-	    fprintf(stderr, "         function correctly. V0.8 was the "
-	                    "last release branch to\n");
-	    fprintf(stderr, "         have active synthesis development "
-	                    "and support!\n");
-      }
-
 	/* Make a common conf file path to reflect the target. */
       snprintf(iconfig_common_path, sizeof iconfig_common_path, "%s%c%s%s.conf",
 	      base, sep, targ, synth_flag? "-s" : "");

elab_expr.cc

@@ -2842,9 +2842,9 @@ NetExpr* PEConcat::elaborate_expr(Design*des, NetScope*scope,
 	    concat->set(idx, parms[off+idx]);
       }
 
-      if (wid_sum == 0 && concat_depth < 2) {
-	    cerr << get_fileline() << ": error: Concatenation may not "
-	         << "have zero width in this context." << endl;
+      if (wid_sum == 0) {
+	    cerr << get_fileline() << ": error: Concatenation/replication "
+	         << "may not have zero width in this context." << endl;
 	    des->errors += 1;
 	    concat_depth -= 1;
 	    delete concat;

elab_scope.cc

@@ -793,7 +793,7 @@ void elaborate_rootscope_tasks(Design*des)
 	    }
 
 	    cerr << cur->second->get_fileline() << ": internal error: "
-		 << "elabortae_rootscope_tasks does not understand "
+		 << "elaborate_rootscope_tasks does not understand "
 		 << "this object," << endl;
 	    des->errors += 1;
       }

elaborate.cc

@@ -4039,9 +4039,18 @@ NetProc* PDisable::elaborate(Design*des, NetScope*scope) const
  */
 NetProc* PDoWhile::elaborate(Design*des, NetScope*scope) const
 {
-      NetExpr*tmp = elab_and_eval(des, scope, cond_, -1);
-      tmp->set_line(*this);
-      NetDoWhile*loop = new NetDoWhile(tmp, statement_->elaborate(des, scope));
+      NetExpr*ce = elab_and_eval(des, scope, cond_, -1);
+      NetProc*sub;
+      if (statement_)
+	    sub = statement_->elaborate(des, scope);
+      else
+	    sub = new NetBlock(NetBlock::SEQU, 0);
+      if (ce == 0 || sub == 0) {
+	    delete ce;
+	    delete sub;
+	    return 0;
+      }
+      NetDoWhile*loop = new NetDoWhile(ce, sub);
       loop->set_line(*this);
       return loop;
 }
@@ -4572,7 +4581,11 @@ NetProc* PEventStatement::elaborate(Design*des, NetScope*scope) const
  */
 NetProc* PForever::elaborate(Design*des, NetScope*scope) const
 {
-      NetProc*stat = statement_->elaborate(des, scope);
+      NetProc*stat;
+      if (statement_)
+	    stat = statement_->elaborate(des, scope);
+      else
+	    stat = new NetBlock(NetBlock::SEQU, 0);
       if (stat == 0) return 0;
 
       NetForever*proc = new NetForever(stat);
@@ -4778,7 +4791,11 @@ NetProc* PForeach::elaborate(Design*des, NetScope*scope) const
 
 	/* Elaborate the statement that is contained in the foreach
 	   loop. */
-      NetProc*sub = statement_->elaborate(des, scope);
+      NetProc*sub;
+      if (statement_)
+	    sub = statement_->elaborate(des, scope);
+      else
+	    sub = new NetBlock(NetBlock::SEQU, 0);
 
 	/* Make a step statement: idx += 1 */
       NetAssign_*idx_lv = new NetAssign_(idx_sig);
@@ -4809,7 +4826,11 @@ NetProc* PForeach::elaborate_static_array_(Design*des, NetScope*scope,
       ivl_assert(*this, index_vars_.size() > 0);
       ivl_assert(*this, dims.size() == index_vars_.size());
 
-      NetProc*sub = statement_->elaborate(des, scope);
+      NetProc*sub;
+      if (statement_)
+	    sub = statement_->elaborate(des, scope);
+      else
+	    sub = new NetBlock(NetBlock::SEQU, 0);
       NetForLoop*stmt = 0;
 
       for (int idx_idx = index_vars_.size()-1 ; idx_idx >= 0 ; idx_idx -= 1) {
@@ -4903,7 +4924,11 @@ NetProc* PForStatement::elaborate(Design*des, NetScope*scope) const
 	   loop. If there is an error, this will return 0 and I should
 	   skip the append. No need to worry, the error has been
 	   reported so it's OK that the netlist is bogus. */
-      NetProc*sub = statement_->elaborate(des, scope);
+      NetProc*sub;
+      if (statement_)
+	    sub = statement_->elaborate(des, scope);
+      else
+	    sub = new NetBlock(NetBlock::SEQU, 0);
 
 	/* Now elaborate the for_step statement. I really should do
 	   some error checking here to make sure the step statement
@@ -5025,7 +5050,11 @@ NetProc* PRepeat::elaborate(Design*des, NetScope*scope) const
       if (expr->expr_type() == IVL_VT_REAL)
 	    expr = cast_to_int4(expr, 64);
 
-      NetProc*stat = statement_->elaborate(des, scope);
+      NetProc*stat;
+      if (statement_)
+	    stat = statement_->elaborate(des, scope);
+      else
+	    stat = new NetBlock(NetBlock::SEQU, 0);
       if (stat == 0) return 0;
 
 	// If the expression is a constant, handle certain special
@@ -5205,7 +5234,11 @@ NetProc* PTrigger::elaborate(Design*des, NetScope*scope) const
 NetProc* PWhile::elaborate(Design*des, NetScope*scope) const
 {
       NetExpr*ce = elab_and_eval(des, scope, cond_, -1);
-      NetProc*sub = statement_->elaborate(des, scope);
+      NetProc*sub;
+      if (statement_)
+	    sub = statement_->elaborate(des, scope);
+      else
+	    sub = new NetBlock(NetBlock::SEQU, 0);
       if (ce == 0 || sub == 0) {
 	    delete ce;
 	    delete sub;

iverilog-vpi.man.in

@@ -1,4 +1,4 @@
-.TH iverilog-vpi 1 "May 10th, 2015" "" "Version %M.%m.%n %E"
+.TH iverilog-vpi 1 "May 10th, 2015" "" "Version %M.%n%E"
 .SH NAME
 iverilog-vpi - Compile front end for VPI modules
 

ivlpp/main.c

@@ -1,5 +1,5 @@
 const char COPYRIGHT[] =
-          "Copyright (c) 1999-2011 Stephen Williams (steve@icarus.com)";
+          "Copyright (c) 1999-2011,2015 Stephen Williams (steve@icarus.com)";
 /*
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU

main.cc

@@ -1,5 +1,5 @@
 const char COPYRIGHT[] =
-          "Copyright (c) 1998-2014 Stephen Williams (steve@icarus.com)";
+          "Copyright (c) 1998-2015 Stephen Williams (steve@icarus.com)";
 
 /*
  *    This source code is free software; you can redistribute it

netlist.cc

@@ -2743,10 +2743,11 @@ DelayType NetCase::delay_type() const
 
       for (unsigned idx = 0; idx < nstmts; idx += 1) {
 	    if (!expr(idx)) def_stmt = true;
+	    DelayType dt = stat(idx) ? stat(idx)->delay_type() : NO_DELAY;
             if (idx == 0) {
-		  result = stat(idx)->delay_type();
+		  result = dt;
             } else {
-		  result = combine_delays(result, stat(idx)->delay_type());
+		  result = combine_delays(result, dt);
             }
       }
 
@@ -2769,6 +2770,7 @@ DelayType NetCondit::delay_type() const
  */
 DelayType NetDoWhile::delay_type() const
 {
+      ivl_assert(*this, proc_);
       return proc_->delay_type();
 }
 
@@ -2779,11 +2781,13 @@ DelayType NetEvWait::delay_type() const
 
 DelayType NetForever::delay_type() const
 {
+      ivl_assert(*this, statement_);
       return statement_->delay_type();
 }
 
 DelayType NetForLoop::delay_type() const
 {
+      ivl_assert(*this, statement_);
       return get_loop_delay_type(condition_, statement_);
 }
 
@@ -2806,6 +2810,7 @@ DelayType NetPDelay::delay_type() const
 
 DelayType NetRepeat::delay_type() const
 {
+      ivl_assert(*this, statement_);
       return get_loop_delay_type(expr_, statement_);
 }
 
@@ -2821,5 +2826,6 @@ DelayType NetUTask::delay_type() const
 
 DelayType NetWhile::delay_type() const
 {
+      ivl_assert(*this, proc_);
       return get_loop_delay_type(cond_, proc_);
 }

pform.cc

@@ -2591,6 +2591,15 @@ void pform_makewire(const struct vlltype&li,
 		    NetNet::Type type,
 		    data_type_t*data_type)
 {
+      if ((lexical_scope == 0) && (generation_flag < GN_VER2005_SV)) {
+	    VLerror(li, "error: variable declarations must be contained within a module.");
+	    return;
+      }
+      if (lexical_scope == 0) {
+	    VLerror(li, "sorry: variable declarations in the $root scope are not yet supported.");
+	    return;
+      }
+
       list<perm_string>*names = new list<perm_string>;
 
       for (list<decl_assignment_t*>::iterator cur = assign_list->begin()
@@ -2887,6 +2896,14 @@ void pform_set_parameter(const struct vlltype&loc,
 			 LexicalScope::range_t*value_range)
 {
       LexicalScope*scope = lexical_scope;
+      if ((scope == 0) && (generation_flag < GN_VER2005_SV)) {
+	    VLerror(loc, "error: parameter declarations must be contained within a module.");
+	    return;
+      }
+      if (scope == 0) {
+	    VLerror(loc, "sorry: parameter declarations in the $root scope are not yet supported.");
+	    return;
+      }
       if (scope == pform_cur_generate) {
             VLerror("parameter declarations are not permitted in generate blocks");
             return;
@@ -2910,7 +2927,7 @@ void pform_set_parameter(const struct vlltype&loc,
 	    error_count += 1;
       }
 	// Only a Module scope has specparams.
-	  if ((dynamic_cast<Module*> (scope)) &&     
+	  if ((dynamic_cast<Module*> (scope)) &&
 		  (scope == pform_cur_module.front()) &&
           (pform_cur_module.front()->specparams.find(name) !=
            pform_cur_module.front()->specparams.end())) {
@@ -2954,7 +2971,14 @@ void pform_set_localparam(const struct vlltype&loc,
 			  bool signed_flag, list<pform_range_t>*range, PExpr*expr)
 {
       LexicalScope*scope = lexical_scope;
-      ivl_assert(loc, scope);
+      if ((scope == 0) && (generation_flag < GN_VER2005_SV)) {
+	    VLerror(loc, "error: localparam declarations must be contained within a module.");
+	    return;
+      }
+      if (scope == 0) {
+	    VLerror(loc, "sorry: localparam declarations in the $root scope are not yet supported.");
+	    return;
+      }
 
 	// Check if the localparam name is already in the dictionary.
       if (scope->localparams.find(name) != scope->localparams.end()) {

scripts/MAKE_RELEASE.sh

@@ -4,7 +4,7 @@
 # the number for a snapshot and the path to a temporary directory.
 # for example:
 #
-#    sh scripts/MAKE_RELEASE.sh 0.9.1 ~/tmp
+#    sh scripts/MAKE_RELEASE.sh 10.1 ~/tmp
 #
 # The above assumes that there is a tag "v0_9_1" at the point
 # to be released. (The tag has the "v", but the argument to this
@@ -13,13 +13,17 @@
 # and finally creates a file called verilog-0.9.1.tar.gz that
 # contains the release ready to go.
 #
-# The complete steps to make a release x.y.z generally are:
+# The complete steps to make a release x.y generally are:
 #
-#   git tag -a v0_9_1
+#   Edit version_base.h to suit.
+#
+#   Edit verilog.spec to suit.
+#
+#   git tag -a v10_1
 #                 (Make the tag in the local git repository.)
 #
-#   sh scripts/MAKE_RELEASE.sh 0.9.1 ~/tmp
-#                 (Make the snapshot bundle verilog-0.9.1.tar.gz)
+#   sh scripts/MAKE_RELEASE.sh 10.1 ~/tmp
+#                 (Make the snapshot bundle verilog-10.1.tar.gz)
 #
 #   git push --tags
 #                 (Publish the tag to the repository.)

tgt-blif/blif.cc

@@ -35,7 +35,7 @@ using namespace std;
 
 static const char*version_string =
 "Icarus Verilog BLIF Code Generator " VERSION " (" VERSION_TAG ")\n\n"
-"Copyright (c) 2013 Stephen Williams (steve@icarus.com)\n\n"
+"Copyright (c) 2013,2015 Stephen Williams (steve@icarus.com)\n\n"
 "  This program is free software; you can redistribute it and/or modify\n"
 "  it under the terms of the GNU General Public License as published by\n"
 "  the Free Software Foundation; either version 2 of the License, or\n"

tgt-null/null.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2000-2015 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -30,7 +30,7 @@
 
 static const char*version_string =
 "Icarus Verilog NULL Code Generator " VERSION " (" VERSION_TAG ")\n\n"
-"Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)\n\n"
+"Copyright (c) 2000-2015 Stephen Williams (steve@icarus.com)\n\n"
 "  This program is free software; you can redistribute it and/or modify\n"
 "  it under the terms of the GNU General Public License as published by\n"
 "  the Free Software Foundation; either version 2 of the License, or\n"

tgt-sizer/sizer.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2014,2015 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -34,7 +34,7 @@ using namespace std;
 
 static const char*version_string =
 "Icarus Verilog SIZER Statistics Generator " VERSION " (" VERSION_TAG ")\n\n"
-"Copyright (c) 2014 Stephen Williams (steve@icarus.com)\n\n"
+"Copyright (c) 2014,2015 Stephen Williams (steve@icarus.com)\n\n"
 "  This program is free software; you can redistribute it and/or modify\n"
 "  it under the terms of the GNU General Public License as published by\n"
 "  the Free Software Foundation; either version 2 of the License, or\n"

tgt-stub/stub.c

@@ -36,7 +36,7 @@
 
 static const char*version_string =
 "Icarus Verilog STUB Code Generator " VERSION " (" VERSION_TAG ")\n\n"
-"Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)\n\n"
+"Copyright (c) 2000-2015 Stephen Williams (steve@icarus.com)\n\n"
 "  This program is free software; you can redistribute it and/or modify\n"
 "  it under the terms of the GNU General Public License as published by\n"
 "  the Free Software Foundation; either version 2 of the License, or\n"

tgt-vlog95/vlog95.c

@@ -30,7 +30,7 @@
 
 static const char*version_string =
 "Icarus Verilog VLOG95 Code Generator " VERSION " (" VERSION_TAG ")\n\n"
-"Copyright (C) 2010-2013 Cary R. (cygcary@yahoo.com)\n\n"
+"Copyright (C) 2010-2015 Cary R. (cygcary@yahoo.com)\n\n"
 "  This program is free software; you can redistribute it and/or modify\n"
 "  it under the terms of the GNU General Public License as published by\n"
 "  the Free Software Foundation; either version 2 of the License, or\n"

tgt-vvp/vvp.c

@@ -28,7 +28,7 @@
 
 static const char*version_string =
 "Icarus Verilog VVP Code Generator " VERSION " (" VERSION_TAG ")\n\n"
-"Copyright (c) 2001-2011 Stephen Williams (steve@icarus.com)\n\n"
+"Copyright (c) 2001-2015 Stephen Williams (steve@icarus.com)\n\n"
 "  This program is free software; you can redistribute it and/or modify\n"
 "  it under the terms of the GNU General Public License as published by\n"
 "  the Free Software Foundation; either version 2 of the License, or\n"

verilog.spec

@@ -1,6 +1,6 @@
 #norootforbuild
 #
-%define rev_date 20150603
+%define rev_date 20150815
 # Normally, the suff-ix is %nil, meaning the suffix is to not be used.
 # But if the builder wants to make a suffixed package, he may set this
 # to a value (i.e. -test) to cause suffixes to be put in all the right
@@ -10,11 +10,11 @@
 #
 Summary: Icarus Verilog
 Name: verilog%{suff}
-Version: 0.10.0.%{rev_date}
+Version: 10.0
 Release: 0
 License: GPL
 Group: Productivity/Scientific/Electronics
-Source: verilog%{suff}-%{rev_date}.tar.gz
+Source: verilog%{suff}-%{version}.tar.gz
 URL: http://www.icarus.com/eda/verilog/index.html
 Packager: Stephen Williams <steve@icarus.com>
 
@@ -32,7 +32,7 @@ engineering formats, including simulation. It strives to be true
 to the IEEE-1364 standard.
 
 %prep
-%setup -n verilog%{suff}-%{rev_date}
+%setup -n verilog-%{version}
 
 %build
 if test X%{suff} != X

version.c

@@ -29,10 +29,7 @@ static void run_string(const char*txt)
 	    if (cp[0] == '%' && cp[1] != 0) {
 		  switch (cp[1]) {
 		      case 'M':
-			fprintf(stdout, "%u", VERSION_MAJOR1);
-			break;
-		      case 'm':
-			fprintf(stdout, "%u", VERSION_MAJOR2);
+			fprintf(stdout, "%u", VERSION_MAJOR);
 			break;
 		      case 'n':
 			fprintf(stdout, "%u", VERSION_MINOR);

version_base.h

@@ -3,17 +3,17 @@
  * Edit this definition in version_base.in to define the base version
  * number for the compiled result.
  */
-# define VERSION_MAJOR1  0
-# define VERSION_MAJOR2  10
+# define VERSION_MAJOR  10
 # define VERSION_MINOR   0
-# define VERSION_EXTRA   "(devel)"
 
-/* This is a concatenation of MAJOR1.MAJOR2 that is used by
-   vams_simparam.c to make a double value. */
-# define VERSION_MAJOR   0.10
+/*
+ * This will be appended to the version. Use this to mark development
+ * versions and the like.
+ */
+# define VERSION_EXTRA   " (stable)"
 
 # define VERSION_STRINGIFY(x) #x
-# define VERSION_STR(a,b,extra) VERSION_STRINGIFY(a.b) " " extra
+# define VERSION_STR(a,b,extra) VERSION_STRINGIFY(a.b) extra
 
 #define VERSION VERSION_STR(VERSION_MAJOR,VERSION_MINOR,VERSION_EXTRA)
 #endif

vhdlpp/expression_elaborate.cc

@@ -874,7 +874,7 @@ const VType* ExpName::probe_prefix_type_(Entity*ent, ScopeBase*scope) const
 }
 
 /*
- * This method is the probe_type() imlementation for ExpName objects
+ * This method is the probe_type() implementation for ExpName objects
  * that have prefix parts. In this case we try to get the type of the
  * prefix and interpret the name in that context.
  */

vhdlpp/main.cc

@@ -38,7 +38,7 @@ const char COPYRIGHT[] =
  *        information to the file named <path>.
  *
  *     elaboration=<path>
- *        Enable debugging of elaboratin by dumping elaboration
+ *        Enable debugging of elaboration by dumping elaboration
  *        process information to the file named <path>.
  *
  *     entities=<path>

vhdlpp/parse.y

@@ -834,14 +834,14 @@ else_when_waveform
 concurrent_signal_assignment_statement /* IEEE 1076-2008 P11.6 */
   : concurrent_simple_signal_assignment
 
-  | IDENTIFIER ':' concurrent_simple_signal_assignment 
+  | IDENTIFIER ':' concurrent_simple_signal_assignment
       { delete[] $1;
 	$$ = $3;
       }
 
   | concurrent_conditional_signal_assignment
 
-  | IDENTIFIER ':' concurrent_conditional_signal_assignment 
+  | IDENTIFIER ':' concurrent_conditional_signal_assignment
       { delete[] $1;
 	$$ = $3;
       }

vhdlpp/scope.h

@@ -169,7 +169,7 @@ class ActiveScope : public ScopeBase {
       bool is_vector_name(perm_string name) const;
 
 	// Locate the subprogram by name. The subprogram body uses
-	// this to locate the sobprogram declaration. Note that the
+	// this to locate the subprogram declaration. Note that the
 	// subprogram may be in a package header.
       SubprogramHeader* recall_subprogram(perm_string name) const;
 

vpi/vhdl_table.c

@@ -156,7 +156,7 @@ static PLI_INT32 ivlh_attribute_event_calltf(ICARUS_VPI_CONST PLI_BYTE8*data)
 
 	    rval.value.scalar = vpi1;
 
-	    // Detect if change occured in this moment
+	    // Detect if change occurred in this moment
 	    if (mon->last_event.high != tnow.high)
 		  rval.value.scalar = vpi0;
 	    if (mon->last_event.low != tnow.low)

vvp/dff.h

@@ -33,7 +33,7 @@
  *   port-2:  Clock Enable input
  *   port-3:  Asynchronous Set/Clear input.
  *
- * The base vvp_dff does not implement an asychronous set/clear.
+ * The base vvp_dff does not implement an asynchronous set/clear.
  */
 class vvp_dff : public vvp_net_fun_t {
 

vvp/examples/assign_reg.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/copy.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/disable.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/edge.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/fork.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/hello.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/hello2.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/memory.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ; Copyright (c) 2001  Stephan Boettcher <stephan@nevis.columbia.edu>
 ;
 ;    This program is free software; you can redistribute it and/or modify

vvp/examples/set_reg.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/sum.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/time.vvp

@@ -1,7 +1,7 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
-; Copyright (c) 2001-2014  Stephen Williams (steve@icarus.com)
+; Copyright (c) 2001-2015  Stephen Williams (steve@icarus.com)
 ;
 ;    This program is free software; you can redistribute it and/or modify
 ;    it under the terms of the GNU General Public License as published by

vvp/examples/vector.vvp

@@ -1,4 +1,4 @@
-:ivl_version "0.10.0" "vec4-stack";
+:ivl_version "10.0" "vec4-stack";
 :vpi_module "system";
 
 ;    This program is free software; you can redistribute it and/or modify

vvp/main.cc

@@ -141,46 +141,44 @@ void verify_version(char*ivl_ver, char*commit)
       }
       delete[] commit;
 
-      char*vvp_ver = strdup(VERSION);
-      char *vp, *ip;
+      int file_major, file_minor, file_minor2;
+      char file_extra[128];
 
-	/* Check the major/minor version. */
-      ip = strrchr(ivl_ver, '.');
-      *ip = '\0';
-      vp = strrchr(vvp_ver, '.');
-      *vp = '\0';
-      if (strcmp(ivl_ver, vvp_ver) != 0) {
-	    vpi_mcd_printf(1, "Error: VVP input file version %s can not "
-	                      "be run with run time version %s!\n",
-	                      ivl_ver, vvp_ver);
+	// Old style format: 0.<major>.<minor> <extra>
+	// This also catches a potential new-new format that has
+	// another sub-minor number.
+      file_extra[0] = 0;
+      int rc = sscanf(ivl_ver, "%d.%d.%d %128s", &file_major, &file_minor, &file_minor2, file_extra);
+
+	// If it wasn't the old style format, try the new format:
+	// <major>.<minor> <extra>
+      if (rc == 2) {
+	    file_extra[0] = 0;
+	    rc = sscanf(ivl_ver, "%d.%d %128s", &file_major, &file_minor, file_extra);
+	    file_minor2 = 0;
+      }
+
+	// If this was the old format, the file_major will be 0. In
+	// this case it is not really what we meant, so convert to the
+	// new format.
+      if (file_major == 0) {
+	    file_major = file_minor;
+	    file_minor = file_minor2;
+	    file_minor2 = 0;
+      }
+
+      if (VERSION_MAJOR != file_major) {
+	    vpi_mcd_printf(1, "Error: VVP input file %d.%d can not "
+			   "be run with run time version %s\n",
+			   file_major, file_minor, VERSION);
 	    exit(1);
       }
 
-	/* Check that the sub-version is compatible. */
-      ip += 1;
-      vp += 1;
-      int ivl_sv, vvp_sv;
-      if (strcmp(ip, "devel") == 0) {
-	    ivl_sv = -1;
-      } else {
-	    int res = sscanf(ip, "%d", &ivl_sv);
-	    assert(res == 1);
+      if (VERSION_MINOR < file_minor) {
+	    vpi_mcd_printf(1, "Warning: VVP input file sub version %d.%d"
+			   " is greater than the run time version %s.\n",
+			   file_major, file_minor, VERSION);
       }
-      if (strcmp(vp, "devel") == 0) {
-	    vvp_sv = -1;
-      } else {
-	    int res = sscanf(vp, "%d", &vvp_sv);
-	    assert(res == 1);
-      }
-      if (ivl_sv > vvp_sv) {
-	    if (verbose_flag) vpi_mcd_printf(1, " ... ");
-	    vpi_mcd_printf(1, "Warning: VVP input file sub-version %s is "
-	                      "greater than the run time sub-version %s!\n",
-	                      ip, vp);
-      }
-
-      delete[] ivl_ver;
-      free(vvp_ver);
 }
 
 int vpip_delay_selection = _vpiDelaySelTypical;
@@ -376,7 +374,7 @@ int main(int argc, char*argv[])
       if (version_flag) {
 	    fprintf(stderr, "Icarus Verilog runtime version " VERSION " ("
 	                    VERSION_TAG ")\n\n");
-	    fprintf(stderr, "Copyright 1998-2012 Stephen Williams\n\n");
+	    fprintf(stderr, "Copyright 1998-2015 Stephen Williams\n\n");
 	    fprintf(stderr,
 "  This program is free software; you can redistribute it and/or modify\n"
 "  it under the terms of the GNU General Public License as published by\n"

vvp/vvp.man.in

@@ -1,4 +1,4 @@
-.TH vvp 1 "May 10th, 2015" "" "Version %M.%m.%n %E"
+.TH vvp 1 "May 10th, 2015" "" "Version %M.%n %E"
 .SH NAME
 vvp - Icarus Verilog vvp runtime engine