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Got sense of tranvp wrong in connections to module ports.

This commit is contained in:
Stephen Williams 2008-06-03 17:23:01 -07:00
parent 73e2b297df
commit ff9166d4a5
2 changed files with 4 additions and 4 deletions
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6
elaborate.cc
View File

@ -901,11 +901,11 @@ NetNet*PGModule::resize_net_to_port_(Design*des, NetScope*scope,
part_b? widb : wida, part_b? widb : wida,
0); 0);
if (part_b) { if (part_b) {
connect(node->pin(0), tmp->pin(0));
connect(node->pin(1), sig->pin(0));
} else {
connect(node->pin(0), sig->pin(0)); connect(node->pin(0), sig->pin(0));
connect(node->pin(1), tmp->pin(0)); connect(node->pin(1), tmp->pin(0));
} else {
connect(node->pin(0), tmp->pin(0));
connect(node->pin(1), sig->pin(0));
} }
node->set_line(*this); node->set_line(*this);

2
tgt-stub/switches.c
View File

@ -53,7 +53,7 @@ void show_switch(ivl_switch_t net)
has_enable = 1; has_enable = 1;
break; break;
case IVL_SW_TRAN_VP: case IVL_SW_TRAN_VP:
fprintf(out, " tran(PV wid=%u, part=%u, off=%u) %s", fprintf(out, " tran(VP wid=%u, part=%u, off=%u) %s",
ivl_switch_width(net), ivl_switch_part(net), ivl_switch_width(net), ivl_switch_part(net),
ivl_switch_offset(net), name); ivl_switch_offset(net), name);
break; break;