Further fixes for vvp code generation for c. assign of an array word.
The draw_net_input() function can write additional statements to the output
file, so must not be called in the midst of writing a statement.
(cherry picked from commit e53b2e774b)
This commit is contained in:
Martin Whitaker
parent
92e4597607
commit
ff21f02c6c
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@ -0,0 +1,34 @@
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module tb();
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reg inputs[1:0];
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reg out;
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always @* begin
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if (inputs[1]) out = inputs[0];
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end
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reg failed;
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(* ivl_synthesis_off *)
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initial begin
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failed = 0;
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#1 inputs[1] = 1;
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#1 inputs[0] = 0;
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#1 $display(inputs[1],,inputs[0],,out);
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if (out !== 0) failed = 1;
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#1 inputs[1] = 0;
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#1 inputs[0] = 1;
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#1 $display(inputs[1],,inputs[0],,out);
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if (out !== 0) failed = 1;
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#1 inputs[1] = 1;
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#1 $display(inputs[1],,inputs[0],,out);
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if (out !== 1) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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@ -0,0 +1,30 @@
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module tb();
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reg [7:0] in[1:0];
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wire [7:0] out[1:0];
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assign out[0] = $clog2(in[0]);
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assign out[1] = $clog2(in[1]);
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reg failed;
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initial begin
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failed = 0;
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#1 in[0] = 1;
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#1 $display("%0d -> %0d", in[0],out[0]);
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if (out[0] !== 0) failed = 1;
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#1 in[1] = 2;
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#1 $display("%0d -> %0d", in[1],out[1]);
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if (out[1] !== 1) failed = 1;
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#1 in[0] = 3;
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#1 $display("%0d -> %0d", in[0],out[0]);
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if (out[0] !== 2) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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@ -342,6 +342,8 @@ br_gh531 normal ivltests gold=br_gh531.gold
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br_gh533 CE ivltests
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br_gh567 normal,-g2001 ivltests gold=br_gh567.gold
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br_gh632 normal ivltests
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br_gh632b normal,-S ivltests
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br_gh632c normal ivltests
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br_ml20150315 normal ivltests gold=br_ml_20150315.gold
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br_ml20150321 CE ivltests
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br_ml20150606 normal ivltests
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@ -1748,6 +1748,11 @@ static void draw_lpm_concat(ivl_lpm_t net)
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static void draw_lpm_ff(ivl_lpm_t net)
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{
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ivl_nexus_t nex;
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const char*clk_in;
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const char*d_in;
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const char*e_in;
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const char*clr_in;
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const char*set_in;
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/* Sync set/clear control is not currently supported. This is not
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* a problem, as synthesis can incorporate this in the D input
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@ -1760,12 +1765,47 @@ static void draw_lpm_ff(ivl_lpm_t net)
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unsigned width = ivl_lpm_width(net);
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char*edge = ivl_lpm_negedge(net) ? "n" : "p";
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if (ivl_lpm_async_clr(net)) {
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nex = ivl_lpm_clk(net);
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assert(nex);
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assert(width_of_nexus(nex) == 1);
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clk_in = draw_net_input(nex);
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nex = ivl_lpm_data(net,0);
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assert(nex);
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assert(width_of_nexus(nex) == width);
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d_in = draw_net_input(nex);
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nex = ivl_lpm_enable(net);
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if (nex) {
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assert(width_of_nexus(nex) == 1);
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e_in = draw_net_input(nex);
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} else {
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e_in = ", C4<1>";
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}
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nex = ivl_lpm_async_clr(net);
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if (nex) {
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assert(width_of_nexus(nex) == 1);
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clr_in = draw_net_input(nex);
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} else {
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clr_in = 0;
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}
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nex = ivl_lpm_async_set(net);
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if (nex) {
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assert(width_of_nexus(nex) == 1);
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set_in = draw_net_input(nex);
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} else {
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set_in = 0;
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}
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if (clr_in) {
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/* Synthesis doesn't currently support both set and clear.
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If it ever does, it might be better to implement the
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flip-flop as a UDP. See tgt-vlog95 for an example of
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how to do this. */
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if (ivl_lpm_async_set(net)) {
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if (set_in) {
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fprintf(stderr, "%s:%u:vvp.tgt: sorry: No support for a DFF "
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"with both an async. set and clear.\n",
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ivl_lpm_file(net), ivl_lpm_lineno(net));
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@ -1778,33 +1818,15 @@ static void draw_lpm_ff(ivl_lpm_t net)
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fprintf(vvp_out, "L_%p .dff/%s %u ", net, edge, width);
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}
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nex = ivl_lpm_data(net,0);
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assert(nex);
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fprintf(vvp_out, "%s", draw_net_input(nex));
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assert(width_of_nexus(nex) == width);
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fprintf(vvp_out, "%s, %s, %s", d_in, clk_in, e_in);
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nex = ivl_lpm_clk(net);
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assert(nex);
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assert(width_of_nexus(nex) == 1);
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fprintf(vvp_out, ", %s", draw_net_input(nex));
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nex = ivl_lpm_enable(net);
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if (nex) {
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assert(width_of_nexus(nex) == 1);
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fprintf(vvp_out, ", %s", draw_net_input(nex));
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} else {
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fprintf(vvp_out, ", C4<1>");
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if (clr_in) {
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fprintf(vvp_out, ", %s", clr_in);
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}
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if ( (nex = ivl_lpm_async_clr(net)) ) {
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assert(width_of_nexus(nex) == 1);
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fprintf(vvp_out, ", %s", draw_net_input(nex));
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}
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if ( (nex = ivl_lpm_async_set(net)) ) {
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if (set_in) {
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ivl_expr_t val = ivl_lpm_aset_value(net);
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assert(width_of_nexus(nex) == 1);
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fprintf(vvp_out, ", %s", draw_net_input(nex));
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fprintf(vvp_out, ", %s", set_in);
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if (val) {
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unsigned nbits = ivl_expr_width(val);
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const char*bits = ivl_expr_bits(val);
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@ -1828,21 +1850,22 @@ static void draw_lpm_ff(ivl_lpm_t net)
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static void draw_lpm_latch(ivl_lpm_t net)
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{
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ivl_nexus_t nex;
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const char*d_in;
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const char*e_in;
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unsigned width = ivl_lpm_width(net);
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fprintf(vvp_out, "L_%p .latch %u ", net, width);
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nex = ivl_lpm_data(net,0);
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assert(nex);
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fprintf(vvp_out, "%s", draw_net_input(nex));
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assert(width_of_nexus(nex) == width);
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d_in = draw_net_input(nex);
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nex = ivl_lpm_enable(net);
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assert(nex);
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assert(width_of_nexus(nex) == 1);
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fprintf(vvp_out, ", %s", draw_net_input(nex));
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e_in = draw_net_input(nex);
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fprintf(vvp_out, ";\n");
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fprintf(vvp_out, "L_%p .latch %u %s, %s;\n", net, width, d_in, e_in);
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}
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static void draw_lpm_shiftl(ivl_lpm_t net)
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@ -1932,6 +1955,13 @@ static void draw_lpm_sfunc(ivl_lpm_t net)
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ivl_variable_type_t dt = data_type_of_nexus(ivl_lpm_q(net));
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const char*dly = draw_lpm_output_delay(net, dt);
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/* Get all the input labels that I will use for net signals that
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connect to the inputs of the function. */
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unsigned ninp = ivl_lpm_size(net);
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const char**input_strings = calloc(ninp, sizeof(char*));
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for (idx = 0 ; idx < ninp ; idx += 1)
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input_strings[idx] = draw_net_input(ivl_lpm_data(net, idx));
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/* Because vvp uses a wide functor for the output of a system
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* function we need to define the output delay net when needed,
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* otherwise it will not be cleaned up correctly (gives a
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@ -1967,7 +1997,7 @@ static void draw_lpm_sfunc(ivl_lpm_t net)
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fprintf(vvp_out, "\"");
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for (idx = 0 ; idx < ivl_lpm_size(net) ; idx += 1) {
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fprintf(vvp_out, ", %s", draw_net_input(ivl_lpm_data(net,idx)));
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fprintf(vvp_out, ", %s", input_strings[idx]);
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}
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fprintf(vvp_out, ";\n");
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@ -2059,6 +2089,7 @@ static void draw_lpm_part(ivl_lpm_t net)
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unsigned width, base;
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ivl_nexus_t sel;
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const char*input = draw_net_input(ivl_lpm_data(net, 0));
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const char*dly = draw_lpm_output_delay(net, IVL_VT_LOGIC);
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width = ivl_lpm_width(net);
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@ -2066,14 +2097,13 @@ static void draw_lpm_part(ivl_lpm_t net)
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sel = ivl_lpm_data(net,1);
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if (sel == 0) {
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fprintf(vvp_out, "L_%p%s .part %s",
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net, dly, draw_net_input(ivl_lpm_data(net, 0)));
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fprintf(vvp_out, "L_%p%s .part %s", net, dly, input);
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fprintf(vvp_out, ", %u, %u;\n", base, width);
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} else {
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const char*sel_symbol = draw_net_input(sel);
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fprintf(vvp_out, "L_%p%s .part/v%s %s", net, dly,
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(ivl_lpm_signed(net) ? ".s" : ""),
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draw_net_input(ivl_lpm_data(net,0)));
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input);
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fprintf(vvp_out, ", %s", sel_symbol);
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fprintf(vvp_out, ", %u;\n", width);
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}
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@ -2089,9 +2119,9 @@ static void draw_lpm_part_pv(ivl_lpm_t net)
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unsigned base = ivl_lpm_base(net);
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unsigned signal_width = width_of_nexus(ivl_lpm_q(net));
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fprintf(vvp_out, "L_%p .part/pv %s",
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net, draw_net_input(ivl_lpm_data(net, 0)));
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const char*input = draw_net_input(ivl_lpm_data(net, 0));
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fprintf(vvp_out, "L_%p .part/pv %s", net, input);
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fprintf(vvp_out, ", %u, %u, %u;\n", base, width, signal_width);
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}
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@ -2100,28 +2130,28 @@ static void draw_lpm_part_pv(ivl_lpm_t net)
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*/
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static void draw_lpm_re(ivl_lpm_t net, const char*type)
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{
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const char*input = draw_net_input(ivl_lpm_data(net, 0));
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const char*dly = draw_lpm_output_delay(net, IVL_VT_LOGIC);
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fprintf(vvp_out, "L_%p%s .reduce/%s %s;\n", net, dly,
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type, draw_net_input(ivl_lpm_data(net,0)));
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fprintf(vvp_out, "L_%p%s .reduce/%s %s;\n", net, dly, type, input);
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}
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static void draw_lpm_repeat(ivl_lpm_t net)
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{
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const char*input = draw_net_input(ivl_lpm_data(net, 0));
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const char*dly = draw_lpm_output_delay(net, IVL_VT_LOGIC);
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fprintf(vvp_out, "L_%p%s .repeat %u, %u, %s;\n", net, dly,
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ivl_lpm_width(net), ivl_lpm_size(net),
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draw_net_input(ivl_lpm_data(net,0)));
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ivl_lpm_width(net), ivl_lpm_size(net), input);
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}
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static void draw_lpm_sign_ext(ivl_lpm_t net)
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{
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const char*input = draw_net_input(ivl_lpm_data(net, 0));
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const char*dly = draw_lpm_output_delay(net, IVL_VT_LOGIC);
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fprintf(vvp_out, "L_%p%s .extend/s %u, %s;\n",
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net, dly, ivl_lpm_width(net),
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draw_net_input(ivl_lpm_data(net,0)));
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net, dly, ivl_lpm_width(net), input);
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}
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static void draw_lpm_in_scope(ivl_lpm_t net)
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