Add new virtex2 architecture family, and

also the new edif.h EDIF management functions.

tgt-fpga/Makefile.in

@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.7 2003/02/27 22:13:22 steve Exp $"
+#ident "$Id: Makefile.in,v 1.8 2003/03/24 00:47:54 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -52,8 +52,8 @@ dep:
 	$(CC) -Wall @ident_support@ -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
 	mv $*.d dep
 
-D = d-generic.o d-generic-edif.o d-virtex.o
+D = d-generic.o d-generic-edif.o d-virtex.o d-virtex2.o
-O = fpga.o gates.o mangle.o tables.o $D
+O = edif.o fpga.o gates.o mangle.o tables.o $D
 
 ifeq (@WIN32@,yes)
   TGTLDFLAGS=-L.. -livl

tgt-fpga/edif.c

@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 200Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: edif.c,v 1.1 2003/03/24 00:47:54 steve Exp $"
+#endif
+
+# include  "edif.h"
+# include  <stdlib.h>
+# include  <string.h>
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+# include  <assert.h>
+
+struct cellref_property_ {
+      const char*name;
+      const char*value;
+      struct cellref_property_*next;
+};
+
+struct edif_s {
+      const char*name;
+	/* List the ports of the design. */
+      unsigned nports;
+      struct __cell_port*ports;
+	/* All the external libraries attached to me. */
+      edif_xlibrary_t xlibs;
+	/* list the cellref instances. */
+      edif_cellref_t celref;
+	/* The root instance has cellref properties as well. */
+      struct cellref_property_*property;
+	/* Keep a list of all the nexa */
+      struct edif_joint_s*nexa;
+};
+
+struct edif_xlibrary_s {
+	/* Name of this library. */
+      const char*name;
+	/* The cells that are contained in this library. */
+      struct edif_cell_s*cells;
+
+	/* used to list libraries in an edif_t. */
+      struct edif_xlibrary_s*next;
+};
+
+
+struct __cell_port {
+      const char*name;
+      ivl_signal_port_t dir;
+};
+
+struct edif_cell_s {
+      const char*name;
+      edif_xlibrary_t xlib;
+
+      unsigned nports;
+      struct __cell_port*ports;
+
+      struct edif_cell_s*next;
+};
+
+struct edif_cellref_s {
+      struct edif_cell_s* cell;
+      unsigned u;
+      struct cellref_property_*property;
+      struct edif_cellref_s* next;
+};
+
+struct joint_cell_ {
+      struct edif_cellref_s*cell;
+      unsigned port;
+      struct joint_cell_*next;
+};
+
+struct edif_joint_s {
+      struct joint_cell_*links;
+      struct edif_joint_s*next;
+};
+
+edif_t edif_create(const char*design_name, unsigned nports)
+{
+      edif_t edf = malloc(sizeof(struct edif_s));
+
+      edf->name  = design_name;
+      edf->nports= nports;
+      edf->ports = nports? calloc(nports, sizeof(struct __cell_port)) : 0;
+      edf->celref= 0;
+      edf->xlibs = 0;
+      edf->property = 0;
+      edf->nexa  = 0;
+
+      return edf;
+}
+
+void edif_portconfig(edif_t edf, unsigned idx,
+		     const char*name, ivl_signal_port_t dir)
+{
+      assert(idx < edf->nports);
+
+      edf->ports[idx].name = name;
+      edf->ports[idx].dir  = dir;
+}
+
+void edif_port_to_joint(edif_joint_t jnt, edif_t edf, unsigned port)
+{
+      struct joint_cell_* jc = malloc(sizeof(struct joint_cell_));
+
+      jc->cell = 0;
+      jc->port = port;
+      jc->next = jnt->links;
+      jnt->links = jc;
+}
+
+void edif_pstring(edif_t edf, const char*name, const char*value)
+{
+      struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
+      prp->name = name;
+      prp->value = value;
+      prp->next = edf->property;
+      edf->property = prp;
+}
+
+edif_xlibrary_t edif_xlibrary_create(edif_t edf, const char*name)
+{
+      edif_xlibrary_t xlib = malloc(sizeof(struct edif_xlibrary_s));
+
+      xlib->name = name;
+      xlib->cells= 0;
+      xlib->next = edf->xlibs;
+      edf->xlibs = xlib;
+
+      return xlib;
+}
+
+edif_cell_t edif_xlibrary_findcell(edif_xlibrary_t xlib,
+				   const char*cell_name)
+{
+      edif_cell_t cur;
+      for (cur = xlib->cells ;  cur ;  cur = cur->next) {
+	    if (strcmp(cell_name, cur->name) == 0)
+		  return cur;
+      }
+
+      return 0;
+}
+
+edif_cell_t edif_xcell_create(edif_xlibrary_t xlib, const char*name,
+			      unsigned nports)
+{
+      unsigned idx;
+      edif_cell_t cell = malloc(sizeof(struct edif_cell_s));
+
+      cell->name = name;
+      cell->xlib = xlib;
+      cell->nports = nports;
+      cell->ports  = calloc(nports, sizeof(struct __cell_port));
+
+      for (idx = 0 ;  idx < nports ;  idx += 1) {
+	    cell->ports[idx].name = "?";
+	    cell->ports[idx].dir = IVL_SIP_NONE;
+      }
+
+      cell->next = xlib->cells;
+      xlib->cells = cell;
+
+      return cell;
+}
+
+void edif_cell_portconfig(edif_cell_t cell, unsigned idx,
+			  const char*name, ivl_signal_port_t dir)
+{
+      assert(idx < cell->nports);
+
+      cell->ports[idx].name = name;
+      cell->ports[idx].dir  = dir;
+}
+
+unsigned edif_cell_port_byname(edif_cell_t cell, const char*name)
+{
+      unsigned idx = 0;
+      for (idx = 0 ;  idx < cell->nports ;  idx += 1)
+	    if (strcmp(name, cell->ports[idx].name) == 0)
+		  break;
+
+      return idx;
+}
+
+edif_cellref_t edif_cellref_create(edif_t edf, edif_cell_t cell)
+{
+      static unsigned u_number = 0;
+      edif_cellref_t ref = malloc(sizeof(struct edif_cellref_s));
+
+      u_number += 1;
+
+      assert(cell);
+      assert(edf);
+
+      ref->u = u_number;
+      ref->cell = cell;
+      ref->property = 0;
+      ref->next = edf->celref;
+      edf->celref = ref;
+
+      return ref;
+}
+
+void edif_cellref_pstring(edif_cellref_t ref, const char*name,
+			   const char*value)
+{
+      struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
+      prp->name = name;
+      prp->value = value;
+      prp->next = ref->property;
+      ref->property = prp;
+}
+
+edif_joint_t edif_joint_create(edif_t edf)
+{
+      edif_joint_t jnt = malloc(sizeof(struct edif_joint_s));
+
+      jnt->links = 0;
+      jnt->next  = edf->nexa;
+      edf->nexa  = jnt;
+      return jnt;
+}
+
+edif_joint_t edif_joint_of_nexus(edif_t edf, ivl_nexus_t nex)
+{
+      void*tmp = ivl_nexus_get_private(nex);
+      edif_joint_t jnt;
+
+      if (tmp == 0) {
+	    jnt = edif_joint_create(edf);
+	    ivl_nexus_set_private(nex, jnt);
+	    return jnt;
+      }
+
+      jnt = (edif_joint_t) tmp;
+      return jnt;
+}
+
+void edif_add_to_joint(edif_joint_t jnt, edif_cellref_t cell, unsigned port)
+{
+      struct joint_cell_* jc = malloc(sizeof(struct joint_cell_));
+
+      jc->cell = cell;
+      jc->port = port;
+      jc->next = jnt->links;
+      jnt->links = jc;
+}
+
+
+/*
+ * This function takes all the data structures that have been
+ * assembled by the code generator, and writes them into an EDIF
+ * formatted file.
+ */
+void edif_print(FILE*fd, edif_t edf)
+{
+      edif_xlibrary_t xlib;
+      edif_cell_t cell;
+      edif_cellref_t ref;
+      edif_joint_t jnt;
+      struct cellref_property_*prp;
+      unsigned idx;
+
+      fprintf(fd, "(edif %s\n", edf->name);
+      fprintf(fd, "    (edifVersion 2 0 0)\n");
+      fprintf(fd, "    (edifLevel 0)\n");
+      fprintf(fd, "    (keywordMap (keywordLevel 0))\n");
+      fprintf(fd, "    (status\n");
+      fprintf(fd, "     (written\n");
+      fprintf(fd, "        (timeStamp 0 0 0 0 0 0)\n");
+      fprintf(fd, "        (author \"unknown\")\n");
+      fprintf(fd, "        (program \"Icarus Verilog/fpga.tgt\")))\n");
+      fflush(fd);
+
+      for (xlib = edf->xlibs ;  xlib ;  xlib = xlib->next) {
+
+	    fprintf(fd, "    (external %s "
+		    "(edifLevel 0) "
+		    "(technology (numberDefinition))\n",
+		    xlib->name);
+
+	    for (cell = xlib->cells ;  cell ;  cell = cell->next) {
+		  fprintf(fd, "      (cell %s (cellType GENERIC)\n",
+			  cell->name);
+		  fprintf(fd, "            (view net\n"
+			      "              (viewType NETLIST)\n"
+			      "              (interface");
+
+		  for (idx = 0 ;  idx < cell->nports ;  idx += 1) {
+			struct __cell_port*pp = cell->ports + idx;
+			fprintf(fd, "\n                (port %s", pp->name);
+			switch (pp->dir) {
+			    case IVL_SIP_INPUT:
+			      fprintf(fd, " (direction INPUT)");
+			      break;
+			    case IVL_SIP_OUTPUT:
+			      fprintf(fd, " (direction OUTPUT)");
+			      break;
+			    case IVL_SIP_INOUT:
+			      fprintf(fd, " (direction INOUT)");
+			      break;
+			    default:
+			      break;
+			}
+			fprintf(fd, ")");
+		  }
+
+		  fprintf(fd, ")))\n");
+	    }
+
+	    fprintf(fd, "    )\n"); /* terminate (external ...) sexp */
+      }
+      fflush(fd);
+
+	/* Write out the library header */
+      fprintf(fd, "    (library DESIGN\n");
+      fprintf(fd, "      (edifLevel 0)\n");
+      fprintf(fd, "      (technology (numberDefinition))\n");
+
+	/* The root module is a cell in the library. */
+      fprintf(fd, "      (cell %s\n", edf->name);
+      fprintf(fd, "        (cellType GENERIC)\n");
+      fprintf(fd, "        (view net\n");
+      fprintf(fd, "          (viewType NETLIST)\n");
+      fprintf(fd, "          (interface\n");
+
+      for (idx = 0 ;  idx < edf->nports ;  idx += 1) {
+	    fprintf(fd, "            (port %s ", edf->ports[idx].name);
+	    switch (edf->ports[idx].dir) {
+		case IVL_SIP_INPUT:
+		  fprintf(fd, "(direction INPUT)");
+		  break;
+		case IVL_SIP_OUTPUT:
+		  fprintf(fd, "(direction OUTPUT)");
+		  break;
+		case IVL_SIP_INOUT:
+		  fprintf(fd, "(direction INOUT)");
+		  break;
+		default:
+		  break;
+	    }
+	    fprintf(fd, ")\n");
+      }
+
+      fprintf(fd, "          )\n"); /* end the (interface ) sexp */
+      fflush(fd);
+
+      fprintf(fd, "          (contents\n");
+
+	/* Display all the instances. */
+      for (ref = edf->celref ;  ref ;  ref = ref->next) {
+
+	    assert(ref->cell);
+
+	    fprintf(fd, "(instance U%u (viewRef net "
+		    "(cellRef %s (libraryRef %s)))",
+		    ref->u, ref->cell->name, ref->cell->xlib->name);
+
+	    for (prp = ref->property ;  prp ;  prp = prp->next)
+		  fprintf(fd, " (property %s (string \"%s\"))",
+			  prp->name, prp->value);
+
+	    fprintf(fd, ")\n");
+      }
+
+      fflush(fd);
+
+	/* Display all the joints. */
+      idx = 0;
+      for (jnt = edf->nexa ;  jnt ;  jnt = jnt->next, idx += 1) {
+	    struct joint_cell_*jc;
+	    fprintf(fd, "(net N%u (joined", idx);
+
+	    for (jc = jnt->links ;  jc ;  jc = jc->next) {
+		  if (jc->cell)
+			fprintf(fd, " (portRef %s (instanceRef U%u))",
+				jc->cell->cell->ports[jc->port].name,
+				jc->cell->u);
+		  else
+			fprintf(fd, " (portRef %s)",
+				edf->ports[jc->port].name);
+	    }
+	    fprintf(fd, "))\n");
+      }
+
+      fprintf(fd, "          )\n"); /* end the (contents...) sexp */
+
+      fprintf(fd, "        )\n"); /* end the (view ) sexp */
+      fprintf(fd, "      )\n"); /* end the (cell ) sexp */
+      fprintf(fd, "    )\n"); /* end the (library DESIGN) sexp */
+
+	/* Make an instance of the defined object */
+      fprintf(fd, "    (design %s\n", edf->name);
+      fprintf(fd, "      (cellRef %s (libraryRef DESIGN))\n", edf->name);
+
+      for (prp = edf->property ;  prp ;  prp = prp->next) {
+	    fprintf(fd, "       (property %s (string \"%s\"))\n",
+		    prp->name, prp->value);
+      }
+
+      fprintf(fd, "    )\n");
+
+
+
+      fprintf(fd, ")\n");
+      fflush(fd);
+}
+
+/*
+ * $Log: edif.c,v $
+ * Revision 1.1  2003/03/24 00:47:54  steve
+ *  Add new virtex2 architecture family, and
+ *  also the new edif.h EDIF management functions.
+ *
+ */
+

tgt-fpga/edif.h

@@ -0,0 +1,201 @@
+#ifndef __edif_H
+#define __edif_H
+/*
+ * Copyright (c) 2003 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: edif.h,v 1.1 2003/03/24 00:47:54 steve Exp $"
+#endif
+
+# include  <stdio.h>
+# include  <ivl_target.h>
+
+/*
+ * These types and functions support the task of generating and
+ * writing out an EDIF 2 0 0 netlist. These functions work by
+ * supporting the creation of an in-core netlist of the design, then
+ * writing the netlist out all at once. The library manages cells with
+ * ports, but does not otherwise interpret cells. They have no
+ * contents.
+ *
+ * The general structure of netlist creation is as follows:
+ *
+ *   Create a netlist with edif_create(<name>);
+ *     This creates an edif object that represents the design. The
+ *     design is given a name, and that name becomes the name of the
+ *     single cell that this netlist handles.
+ *
+ *   Add ports to the root with edif_portconfig
+ *     The design may, if it is a macro to be included in a larger
+ *     design, include ports. These are discovered by looking for port
+ *     signals in the root module.
+ *
+ *   Declare external libraries with edif_xlibrary_create
+ *     Normally, this is the single technology library that contains
+ *     the primitive cells that the code generator intendes to
+ *     use. The library is given a name, such as VIRTEX or whatever
+ *     the implementation tools expect. Cells are attached to the
+ *     library later. An edif netlist may include multiple external
+ *     references.
+ *
+ *   Declare primitives with edif_xcell_create and edif_cell_portconfig.
+ *     These functions create CELL TYPES that are attached to an
+ *     external library. The libraries are created by
+ *     edif_xlibrary_create.
+ *
+ *     Cells can be created at any time before their first use. It
+ *     therefore makes the most sense to not create the cell until it
+ *     is certain that they are needed by the design.
+ *
+ *   Create instances and join them up
+ *     The edif_cellref_t objects represent instances of cells, and
+ *     are the devices of the generated netlist. These cellrefs are
+ *     connected together by the use of edif_joint_t joints. The
+ *     joints can be created from ivl_nexus_t objects, or from their
+ *     own ether. This instantiating of cells and joining them
+ *     together that is the most fun. It is the technology specific
+ *     stuff that the code generator does.
+ *
+ *   Finally, print the result with edif_print(fd);
+ *     This function writes the netlist in memory to an EDIF file on
+ *     the stdio stream specified.
+ *
+ * This library is intended to be used once, to build up a netlist and
+ * print it. All the names that are taken as const char* should be
+ * somehow made permanent by the caller. Either they are constant
+ * strings, or they are strduped as necessary to make them
+ * permanent. The library will not duplicate them.
+ */
+
+/* TYPE DECLARATIONS */
+
+/* This represents the entire EDIF design. You only need one of these
+   to hold everything. */
+typedef struct edif_s* edif_t;
+
+/* Each external library of the design gets one of these. */
+typedef struct edif_xlibrary_s* edif_xlibrary_t;
+
+/* This represents a type of cell. */
+typedef struct edif_cell_s* edif_cell_t;
+
+/* A cellref is an *instance* of a cell. */
+typedef struct edif_cellref_s* edif_cellref_t;
+
+/* This represents a generic joint. Cell ports are connected by being
+   associated with a joint. These can be bound to an ivl_nexus_t
+   object, of stand along. */
+typedef struct edif_joint_s* edif_joint_t;
+
+
+/* FUNCTIONS */
+
+
+/* Start a new EDIF design. The design_name will be used as the name
+   of the top-mode module of the design. */
+extern edif_t edif_create(const char*design_name, unsigned nports);
+
+/* macro ports to the design are handled by this library similar to
+   cells. The user creates ports with this function. This function
+   configures the sole "port" of the cell with the name and dir passed
+   in. The direction, in this case, is the *interface* direction. */
+extern void edif_portconfig(edif_t edf, unsigned idx,
+			    const char*name, ivl_signal_port_t dir);
+
+/* This is like edif_add_to_joint, but works with the edif port. */
+extern void edif_port_to_joint(edif_joint_t jnt, edif_t edf, unsigned port);
+
+/* The design may have properties attached to it. These properties
+   will be attached to the instance declared in the footer of the EDIF
+   file. */
+extern void edif_pstring(edif_t edf, const char*name, const char*value);
+
+/* Create an external library and attach it to the edif design. This
+   will lead to a (external ...) declaration of cells that can be used
+   by the design. */
+extern edif_xlibrary_t edif_xlibrary_create(edif_t edf, const char*name);
+
+/* External libraries can be searched for existing cells, given a
+   string name. This function searches for the cell by name, and
+   returns it. */
+extern edif_cell_t edif_xlibrary_findcell(edif_xlibrary_t lib,
+					  const char*cell_name);
+
+/* Create a new cell, attached to the external library. Specify the
+   number of ports that the cell has. The edif_cell_portconfig
+   function is then used to assign name and direction to each of the
+   ports.
+
+   The cell has a number of pins that are referenced by their number
+   from 0 to nports-1. You need to remember the pin numbers for the
+   named ports for use when joining that pin to an edif_joint_t.
+
+   Cellrefs get their port characteristics from the cell that they are
+   created from. So the pinouts of cellrefs match the pinout of the
+   associated cell. */
+extern edif_cell_t edif_xcell_create(edif_xlibrary_t, const char*name,
+				     unsigned nports);
+extern void edif_cell_portconfig(edif_cell_t cell, unsigned idx,
+				 const char*name, ivl_signal_port_t dir);
+
+/* Ports of cells are normally referenced by their port number. If you
+   forget what that number is, this function can look it up by name. */
+extern unsigned edif_cell_port_byname(edif_cell_t cell, const char*name);
+
+
+/* Create and instance from a cell. The instance refers to the cell,
+   which is a type, and contains pips for pins. */
+extern edif_cellref_t edif_cellref_create(edif_t edf, edif_cell_t cell);
+
+/* Instances can have properties attached to them. The name and value
+   given here are turned into a (property <name> (string "val"))
+   sexpression attached to the instance.
+
+   Examples of string properties commonly attached to cellref devices
+   include such things as the INIT=<value> to initialize LUT cells in
+   FPGA devices. */
+extern void edif_cellref_pstring(edif_cellref_t ref, const char*name,
+				 const char*value);
+
+/* This function gets the joint associated with a nexus. This will
+   create a joint if necessary. */
+extern edif_joint_t edif_joint_of_nexus(edif_t edf, ivl_nexus_t nex);
+
+/* For linking cells outside the ivl netlist, this function creates an
+   anonymous joint. */
+extern edif_joint_t edif_joint_create(edif_t edf);
+
+/* Given a joint, this function adds the cell reference. */
+extern void edif_add_to_joint(edif_joint_t jnt,
+			      edif_cellref_t cell,
+			      unsigned port);
+
+/*
+ * Print the entire design. This should only be done after the design
+ * is completely assembled.
+ */
+extern void edif_print(FILE*fd, edif_t design);
+
+/*
+ * $Log: edif.h,v $
+ * Revision 1.1  2003/03/24 00:47:54  steve
+ *  Add new virtex2 architecture family, and
+ *  also the new edif.h EDIF management functions.
+ *
+ */
+#endif

tgt-fpga/fpga.txt

@@ -2,7 +2,7 @@
 FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
 
   Copyright 2001 Stephen Williams
-  $Id: fpga.txt,v 1.5 2002/04/30 04:26:42 steve Exp $
+  $Id: fpga.txt,v 1.6 2003/03/24 00:47:54 steve Exp $
 
 The FPGA code generator supports a variety of FPGA devices, writing
 XNF or EDIF depending on the target. You can select the architecture
@@ -51,6 +51,11 @@ should work properly for any Virtex part.
 
 XNF ROOT PORTS
 
+  NOTE: As parts are moved over to EDIF format, XNF support will be
+  phased out. Current Xilinx implementation tools will accept EDIF
+  format files even for the older parts, and non-Xilinx implementation
+  tools accept nothing else.
+
 When the output format is XNF, the code generator will generate "SIG"
 records for the signals that are ports of the root module. The name is
 declared as an external pin that this macro makes available.
@@ -169,6 +174,10 @@ Compile a single-file design with command line tools like so:
 
 ---
 $Log: fpga.txt,v $
+Revision 1.6  2003/03/24 00:47:54  steve
+ Add new virtex2 architecture family, and
+ also the new edif.h EDIF management functions.
+
 Revision 1.5  2002/04/30 04:26:42  steve
  Spelling errors.
 

tgt-fpga/tables.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: tables.c,v 1.4 2002/08/12 01:35:03 steve Exp $"
+#ident "$Id: tables.c,v 1.5 2003/03/24 00:47:54 steve Exp $"
 #endif
 
 # include  "fpga_priv.h"
@@ -27,6 +27,7 @@
 extern const struct device_s d_generic;
 extern const struct device_s d_generic_edif;
 extern const struct device_s d_virtex_edif;
+extern const struct device_s d_virtex2_edif;
 
 
 const struct device_table_s {
@@ -36,6 +37,7 @@ const struct device_table_s {
       { "generic-edif", &d_generic_edif },
       { "generic-xnf",  &d_generic },
       { "virtex",       &d_virtex_edif },
+      { "virtex2",      &d_virtex2_edif },
       { 0, 0 }
 };
 
@@ -56,6 +58,10 @@ device_t device_from_arch(const char*arch)
 
 /*
  * $Log: tables.c,v $
+ * Revision 1.5  2003/03/24 00:47:54  steve
+ *  Add new virtex2 architecture family, and
+ *  also the new edif.h EDIF management functions.
+ *
  * Revision 1.4  2002/08/12 01:35:03  steve
  *  conditional ident string using autoconfig.
  *