Receive expanded documentation from Steve Wilson.
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README.txt
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README.txt
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THE ICARUS VERILOG COMPILATION SYSTEM
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5/7/99
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THE ICARUS VERILOG COMPILATION SYSTEM
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This tool includes a parser that parses Verilog (plus extensions) and
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1.0 What is ICARUS Verilog(IVL)?
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Icarus Verilog is intended to compile ALL of the Verilog HDL as described
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in the IEEE-1364 standard. Of course, it's not quite there yet. I do
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handle a mix of structural and behavioral constructs.
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IVL is not aimed at being a simulator in the traditional sense, but a
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compiler that generates code employed by back-end tools. These back-
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end tools currently include a simulator written in C++ called VVM
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and an XNF (Xilinx Netlist Format) generator. See "vvm.txt" and
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"xnf.txt" for further details on the back-end processors.
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2.0 How IVL Works
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This tool includes a parser which read in Verilog (plus extensions) and
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generates an internal netlist. The netlist is passed to various
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processing steps that transform the design to more optimal/practical
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forms, then passed to a code generator for final output. The
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processing steps and the code generator are selected by command line
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switches.
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INVOKING ivl
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2.1 Parse
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The vl command is the compiler driver, that invokes the parser,
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The verilog compiler starts by parsing the verilog source file. The
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output of the parse in a list of Module objects in PFORM. The pform
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(see pform.h) is mostly a direct reflection of the compilation
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unit. There may be dangling references, and it is not yet clear which
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module is the root.
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2.2 Elaboration
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This phase takes the pform and generates a netlist. The driver selects
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(by user request or lucky guess) the root module to elaborate,
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resolves references and expands the instantiations to form the design
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netlist.
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The elaborate() function performs the elaboration.
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2.3 Optimization
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This is actually a collection of processing steps that perform
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optimizations that do not depend on the target technology. Examples of
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some useful transformations would be,
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- eliminate null effect circuitry,
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- combinational reduction
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- Constant propagation
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The actual functions performed are specified on the command line by
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the -F flags (See below).
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2.4 Code Generation
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This step takes the design netlist and uses it to drive the code
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generator. (See target.h.) This may require transforming the
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design to suit the technology.
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The emit() method of the Design class performs this step. It runs
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through the design elements, calling target functions as need arises
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to generate actual output.
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The target code generator to used is given by the -t flag on the
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command line.
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3.0 Building/Installing IVL
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Unpack the tar-ball and cd into the verilog-######### directory.
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./configure
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make
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cd vvm
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make
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Now install the files in an appropriate place. (The makefiles by
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default install in /usr/local unless you specify a different prefix
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with the --prefix=<path> flag to the configure command.) Do this as
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root.
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make install
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cd vvm
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make install
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4.0 Running IVL
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The ivl command is the compiler driver, that invokes the parser,
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optimization functions and the code generator.
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Usage: ivl <options>... file
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@ -23,7 +99,7 @@ Usage: ivl <options>... file
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variety of processing steps. The steps will be applied in
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order, with the output of one uses as the input to the next.
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The function is specified by name. Use the "vl -h" command to
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The function is specified by name. Use the "ivl -h" command to
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get a list of configured function names.
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-f <assign>
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@ -34,12 +110,12 @@ Usage: ivl <options>... file
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The useful keys are defined by the functions and the target in
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use. These assignments are specifically useful for passing
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target specific information to the target backend, or
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target specific information to the target back-end, or
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options/parameters to optimization functions, if any are defined.
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-N <file>
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Dump the elaborated netlist to the named file. The netlist is
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the fully elaborated netlist, after all the function modules
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the folly elaborated netlist, after all the function modules
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are applied and right before the output generator is
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called. This is an aid for debugging the compiler, and the
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output generator in particular.
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@ -56,13 +132,13 @@ Usage: ivl <options>... file
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the compiler.
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-s <module>
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Normally, vl will elaborate the only top-level module in the
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source file. If there are multiple modules, use this option to
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select the module to be used as the top-level module.
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Normally, ivl will elaborate the only module in the source
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file. If there are multiple modules, use this option to select
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the module to be used as the top-level module.
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-t <name>
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Select the output format for the compiled result. Use the
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"vl -h" command to get a list of configured targets.
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"ivl -h" command to get a list of configured targets.
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ATTRIBUTES
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@ -96,47 +172,51 @@ between processing steps. Processing steps that are aware of others
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may place attributes on netlist objects to communicate information to
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later steps.
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HOW IT WORKS -- STAGES OF PROCESSING
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4.1 EXAMPLES
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* Parse
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Example: Compiling "hello.vl"
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The verilog compiler starts by parsing the verilog source file. The
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output of the parse in a list of Module objects in PFORM. The pform
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(see pform.h) is mostly a direct reflection of the compilation
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unit. There may be dangling references, and it is not yet clear which
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module is the root.
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------------------------ hello.vl ----------------------------
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module main();
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initial
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begin
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$display("Hi there");
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$finish ;
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end
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* Elaboration
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endmodule
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This phase takes the pform and generates a netlist. The driver selects
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(by user request or lucky guess) the root module to elaborate,
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resolves references and expands the instantiations to form the design
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netlist.
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--------------------------------------------------------------
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The elaborate() function performs the elaboration.
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Insure that "ivl" is on your search path, and the library
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libvvm.a is available.
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* Optimization
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For csh -
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This is actually a collection of processing steps that perform
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optimizations that do not depend on the target technology. Examples of
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some useful transformations would be,
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setenv PATH /usr/local/bin:$PATH
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setenv LD_LIBRARY_PATH /usr/local/lib:$LD_LIBRARY_PATH
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- eliminate null effect circuitry,
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- combinational reduction
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- Constant propogation
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ivl -t vvm -o hello.cc hello.vl
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g++ hello.cc -o hello -lvvm
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The actual functions performed are specified on the command line by
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the -F flags.
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To run the program
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* Code Generation
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./hello
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This step takes the design netlist and uses it to drive the code
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generator. (See target.h.) This may require transforming the
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design to suit the technology.
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The emit() method of the Design class performs this step. It runs
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through the design elements, calling target functions as need arises
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to generate actual output.
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5.0 Unsupported Constructs
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The target code generator to used is given by the -t flag on the
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command line.
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IVL is in development - as such it still only supports a subset
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of verilog. Below is a description of some of the currently unsupported
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verilog features.
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Event Control - ??
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Lvalue bit ranges - Example: regvalue [7:3] = 5'b0;
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Non-blocking Assignment - Example: regvalue <= 5'b0;
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Complex delay expressions - ??
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Tasks/functions
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