Add DFF nodes.

vvp/Makefile.in

@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.65 2005/04/03 06:13:34 steve Exp $"
+#ident "$Id: Makefile.in,v 1.66 2005/04/24 20:07:25 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -82,7 +82,7 @@ vpi_memory.o vpi_vthr_vector.o vpip_bin.o vpip_hex.o vpip_oct.o \
 vpip_to_dec.o vpip_format.o vvp_vpi.o
 
 O = main.o parse.o parse_misc.o lexor.o arith.o bufif.o compile.o concat.o \
-functor.o npmos.o part.o reduce.o resolv.o stop.o symbols.o \
+dff.o functor.o npmos.o part.o reduce.o resolv.o stop.o symbols.o \
 ufunc.o codes.o \
 vthread.o schedule.o statistics.o tables.o udp.o vvp_net.o memory.o \
 force.o event.o logic.o delay.o words.o $V

vvp/README.txt

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
  *
- *  $Id: README.txt,v 1.62 2005/03/19 06:23:49 steve Exp $
+ *  $Id: README.txt,v 1.63 2005/04/24 20:07:26 steve Exp $
  */
 
 VVP SIMULATION ENGINE
@@ -150,6 +150,22 @@ Almost all of the structural aspects of a simulation can be
 represented by functors, which perform the very basic task of
 combining up to four inputs down to one output.
 
+DFF STATEMENTS:
+
+The Verilog language itself does not have a DFF primitive, but post
+synthesis readily creates DFF devices that are best simulated with a
+common device. Thus, there is the DFF statement to create DFF devices:
+
+        <label> .dff <d>, <clk>, <ce>, <async-input>;
+
+The generated functor is generally synchronous on the <clk> rising
+edge of <clk>, with the <ce> enable active high. The <clk> and <ce>
+are single bit vectors (or scalars) on ports 1 and 2. Port-0 is any
+type of datum at all. The device will transfer the input to the output
+when it is loaded by a clock. The <async-input> is a special
+asynchronous input that is immediately stored and transferred to the
+output when data arrives here. This is useful for implementing
+asynchronous set/clear functions.
 
 UDP STATEMENTS:
 
@@ -159,7 +175,7 @@ UDP functor has as many inputs as the UDP definition requires.
 
 UDPs come in sequential and combinatorial flavors.  Sequential UDPs
 carry an output state and can respond to edges at the inputs.  The
-output of a combinatorial UDPs is a function of its current inputs
+output of combinatorial UDPs is a function of its current inputs
 only.
 
 The function of a UDP is defined via a table.  The rows of the table

vvp/compile.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: compile.cc,v 1.196 2005/04/01 06:02:45 steve Exp $"
+#ident "$Id: compile.cc,v 1.197 2005/04/24 20:07:26 steve Exp $"
 #endif
 
 # include  "arith.h"
@@ -1052,7 +1052,6 @@ void compile_cmp_gt(char*label, long wid, bool signed_flag,
       make_arith(arith, label, wid, argc, argv);
 }
 
-
 /*
  * A .shift/l statement creates an array of functors for the
  * width. The 0 input is the data vector to be shifted and the 1 input
@@ -1567,6 +1566,9 @@ void compile_param_string(char*label, char*name, char*str, char*value)
 
 /*
  * $Log: compile.cc,v $
+ * Revision 1.197  2005/04/24 20:07:26  steve
+ *  Add DFF nodes.
+ *
  * Revision 1.196  2005/04/01 06:02:45  steve
  *  Reimplement combinational UDPs.
  *

vvp/compile.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: compile.h,v 1.68 2005/04/03 05:45:51 steve Exp $"
+#ident "$Id: compile.h,v 1.69 2005/04/24 20:07:26 steve Exp $"
 #endif
 
 # include  <stdio.h>
@@ -146,6 +146,11 @@ extern void compile_cmp_ge(char*label, long width, bool signed_flag,
 			   unsigned argc, struct symb_s*argv);
 extern void compile_cmp_gt(char*label, long width, bool signed_flag,
 			   unsigned argc, struct symb_s*argv);
+extern void compile_dff(char*label,
+			struct symb_s arg_d,
+			struct symb_s arg_c,
+			struct symb_s arg_e,
+			struct symb_s arg_a);
 extern void compile_reduce_and(char*label, struct symb_s arg);
 extern void compile_reduce_or(char*label, struct symb_s arg);
 extern void compile_reduce_xor(char*label, struct symb_s arg);
@@ -310,6 +315,9 @@ extern void compile_net(char*label, char*name,
 
 /*
  * $Log: compile.h,v $
+ * Revision 1.69  2005/04/24 20:07:26  steve
+ *  Add DFF nodes.
+ *
  * Revision 1.68  2005/04/03 05:45:51  steve
  *  Rework the vvp_delay_t class.
  *

vvp/dff.cc

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2005 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: dff.cc,v 1.1 2005/04/24 20:07:26 steve Exp $"
+#endif
+
+# include  "compile.h"
+# include  "schedule.h"
+# include  "dff.h"
+# include  <limits.h>
+# include  <stdio.h>
+# include  <assert.h>
+# include  <stdlib.h>
+#ifdef HAVE_MALLOC_H
+# include  <malloc.h>
+#endif
+
+vvp_dff::vvp_dff(bool invert_clk, bool invert_ce)
+: iclk_(invert_clk), ice_(invert_ce)
+{
+      clk_cur_ = BIT4_X;
+}
+
+vvp_dff::~vvp_dff()
+{
+}
+
+void vvp_dff::recv_vec4(vvp_net_ptr_t port, vvp_vector4_t bit)
+{
+      vvp_bit4_t tmp;
+
+      switch (port.port()) {
+
+	  case 0: // D
+	    d_ = bit;
+	    break;
+
+	      /* This is a clock input */
+	  case 1: // CLK
+	    assert(bit.size() == 1);
+	    if (enable_ != BIT4_1)
+		  break;
+	    tmp = clk_cur_;
+	    clk_cur_ = bit.value(0);
+	    if (clk_cur_ == BIT4_1 && tmp != BIT4_1)
+		  vvp_send_vec4(port.ptr()->out, d_);
+	    break;
+
+	  case 2: // CE
+	    assert(bit.size() == 1);
+	    enable_ = bit.value(0);
+	    break;
+
+	  case 3: // Asynch-D
+	    d_ = bit;
+	    vvp_send_vec4(port.ptr()->out, d_);
+	    break;
+      }
+}
+
+void compile_dff(char*label, struct symb_s arg_d,
+		 struct symb_s arg_c,
+		 struct symb_s arg_e,
+		 struct symb_s arg_a)
+{
+      vvp_net_t*ptr = new vvp_net_t;
+      vvp_dff*fun = new vvp_dff(false, false);
+
+      ptr->fun = fun;
+      define_functor_symbol(label, ptr);
+      free(label);
+      input_connect(ptr, 0, arg_d.text);
+      input_connect(ptr, 1, arg_c.text);
+      input_connect(ptr, 2, arg_e.text);
+      input_connect(ptr, 3, arg_a.text);
+}

vvp/dff.h

@@ -0,0 +1,52 @@
+#ifndef __vvp_dff_H
+#define __vvp_dff_H
+/*
+ * Copyright (c) 2005 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ident "$Id: dff.h,v 1.1 2005/04/24 20:07:26 steve Exp $"
+
+# include  "vvp_net.h"
+
+/*
+ * The vvp_dff implements a D-type FF that is agnostic to the data
+ * type that is holds. The clock and clock-enable inputs are single
+ * bits and may be invertable. An output is propagated on the logical
+ * rising edge of the clock input, or whenever an asynchronous input
+ * is received. Ports are:
+ *
+ *   port-0:  D input
+ *   port-1:  Clock input
+ *   port-2:  Clock Enagle input
+ *   port-3:  Asynchronous D input.
+ */
+class vvp_dff  : public vvp_net_fun_t {
+
+    public:
+      explicit vvp_dff(bool invert_clk =false, bool invert_ce =false);
+      ~vvp_dff();
+
+      virtual void recv_vec4(vvp_net_ptr_t port, vvp_vector4_t bit);
+
+    private:
+      bool iclk_, ice_;
+      vvp_bit4_t clk_cur_;
+      vvp_bit4_t enable_;
+      vvp_vector4_t d_;
+};
+
+#endif

vvp/lexor.lex

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: lexor.lex,v 1.50 2005/03/09 05:52:04 steve Exp $"
+#ident "$Id: lexor.lex,v 1.51 2005/04/24 20:07:26 steve Exp $"
 #endif
 
 # include  "parse_misc.h"
@@ -98,6 +98,7 @@
 ".cmp/gt"   { return K_CMP_GT; }
 ".cmp/gt.s" { return K_CMP_GT_S; }
 ".concat"   { return K_CONCAT; }
+".dff"      { return K_DFF; }
 ".event"    { return K_EVENT; }
 ".event/or" { return K_EVENT_OR; }
 ".functor"  { return K_FUNCTOR; }
@@ -194,6 +195,9 @@ int yywrap()
 
 /*
  * $Log: lexor.lex,v $
+ * Revision 1.51  2005/04/24 20:07:26  steve
+ *  Add DFF nodes.
+ *
  * Revision 1.50  2005/03/09 05:52:04  steve
  *  Handle case inequality in netlists.
  *

vvp/parse.y

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: parse.y,v 1.71 2005/04/03 05:45:51 steve Exp $"
+#ident "$Id: parse.y,v 1.72 2005/04/24 20:07:26 steve Exp $"
 #endif
 
 # include  "parse_misc.h"
@@ -61,7 +61,7 @@ extern FILE*yyin;
 %token K_ARITH_SUB K_ARITH_SUM
 %token K_CMP_EEQ K_CMP_EQ K_CMP_NEE K_CMP_NE
 %token K_CMP_GE K_CMP_GE_S K_CMP_GT K_CMP_GT_S
-%token K_CONCAT
+%token K_CONCAT K_DFF
 %token K_EVENT K_EVENT_OR K_FUNCTOR K_NET K_NET_S K_PARAM K_PART K_PART_PV
 %token K_REDUCE_AND K_REDUCE_OR K_REDUCE_XOR
 %token K_REDUCE_NAND K_REDUCE_NOR K_REDUCE_XNOR K_REPEAT
@@ -278,6 +278,13 @@ statement
 		  compile_cmp_gt($1, $3, true, obj.cnt, obj.vect);
 		}
 
+  /* DFF nodes have an output and take exactly 4 inputs. */
+
+        | T_LABEL K_DFF symbol ',' symbol ',' symbol ',' symbol ';'
+                { compile_dff($1, $3, $5, $7, $9); }
+
+  /* The various reduction operator nodes take a single input. */
+
         | T_LABEL K_REDUCE_AND symbol ';'
                 { compile_reduce_and($1, $3); }
 
@@ -679,6 +686,9 @@ int compile_design(const char*path)
 
 /*
  * $Log: parse.y,v $
+ * Revision 1.72  2005/04/24 20:07:26  steve
+ *  Add DFF nodes.
+ *
  * Revision 1.71  2005/04/03 05:45:51  steve
  *  Rework the vvp_delay_t class.
  *