Add define to indicate Icarus synthesis

This commit is contained in:
Cary R 2021-01-14 00:10:09 -08:00
parent e396369410
commit f806ed5084
2 changed files with 12 additions and 5 deletions

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@ -1,4 +1,4 @@
.TH iverilog 1 "Aug 10th, 2020" "" "Version %M.%n%E" .TH iverilog 1 "Jan 14th, 2021" "" "Version %M.%n%E"
.SH NAME .SH NAME
iverilog - Icarus Verilog compiler iverilog - Icarus Verilog compiler
@ -582,9 +582,13 @@ The following macros are predefined by the compiler:
.B __ICARUS__ = 1 .B __ICARUS__ = 1
This is always defined when compiling with Icarus Verilog. This is always defined when compiling with Icarus Verilog.
.TP 8
.B __ICARUS_SYNTH__ = 1
This is defined when synthesis is enabled.
.TP 8 .TP 8
.B __VAMS_ENABLE__ = 1 .B __VAMS_ENABLE__ = 1
This is defined if Verilog\-AMS is enabled. This is defined when Verilog\-AMS is enabled.
.SH ENVIRONMENT .SH ENVIRONMENT
.PP .PP
@ -633,7 +637,7 @@ Tips on using, debugging, and developing the compiler can be found at
.SH COPYRIGHT .SH COPYRIGHT
.nf .nf
Copyright \(co 2002\-2020 Stephen Williams Copyright \(co 2002\-2021 Stephen Williams
This document can be freely redistributed according to the terms of the This document can be freely redistributed according to the terms of the
GNU General Public License version 2.0 GNU General Public License version 2.0

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@ -1116,8 +1116,6 @@ int main(int argc, char **argv)
} }
fprintf(defines_file, "D:__ICARUS__=1\n"); fprintf(defines_file, "D:__ICARUS__=1\n");
if (strcmp(gen_verilog_ams,"verilog-ams") == 0)
fprintf(defines_file, "D:__VAMS_ENABLE__=1\n");
/* Create another temporary file for passing configuration /* Create another temporary file for passing configuration
information to ivl. */ information to ivl. */
@ -1301,6 +1299,11 @@ int main(int argc, char **argv)
} }
} }
if (strcmp(gen_verilog_ams,"verilog-ams") == 0)
fprintf(defines_file, "D:__VAMS_ENABLE__=1\n");
if (synth_flag)
fprintf(defines_file, "D:__ICARUS_SYNTH__=1\n");
if (vpi_dir == 0) if (vpi_dir == 0)
vpi_dir = base; vpi_dir = base;
if (ivlpp_dir == 0) if (ivlpp_dir == 0)