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Handle concatenation of SystemVerilog strings.

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This commit is contained in:
Stephen Williams
2012-07-22 10:52:06 -07:00
parent 2bd3d9ed5d
commit f77bdf7e38
19 changed files with 283 additions and 27 deletions
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net_expr.cc
+9 -4
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@@ -184,18 +184,23 @@ bool NetEBShift::has_width() const
return left_->has_width();
}
NetEConcat::NetEConcat(unsigned cnt, unsigned r)
: parms_(cnt), repeat_(r)
NetEConcat::NetEConcat(unsigned cnt, unsigned r, ivl_variable_type_t vt)
: parms_(cnt), repeat_(r), expr_type_(vt)
{
expr_width(0);
}
NetEConcat::~NetEConcat()
{
for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1)
for (unsigned idx = 0 ; idx < parms_.size() ; idx += 1)
delete parms_[idx];
}
ivl_variable_type_t NetEConcat::expr_type() const
{
return expr_type_;
}
bool NetEConcat::has_width() const
{
return true;
@@ -203,7 +208,7 @@ bool NetEConcat::has_width() const
void NetEConcat::set(unsigned idx, NetExpr*e)
{
assert(idx < parms_.count());
assert(idx < parms_.size());
assert(parms_[idx] == 0);
parms_[idx] = e;
expr_width( expr_width() + repeat_ * e->expr_width() );