Add regression test for issue #1286.

This commit is contained in:
Martin Whitaker 2025-11-11 22:00:06 +00:00
parent 28717b4de7
commit f5708a0322
3 changed files with 44 additions and 0 deletions

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@ -0,0 +1,38 @@
module test;
reg [1:0] a;
reg b;
reg c;
reg d;
always_latch begin
if (a[1])
c = 1;
else if (a[0])
c = 0;
end
always_latch begin
if (b)
d = 1;
else if (a[0])
d = 0;
end
reg failed = 0;
initial begin
$monitor("%0t : %b %b : %b %b", $time, a, b, c, d);
a[0] = 1'b1;
#1 if (c !== 1'b0 && d !== 1'b0) failed = 1;
a[1] = 1'b1;
#1 if (c !== 1'b1 && d !== 1'b0) failed = 1;
b = 1'b1;
#1 if (c !== 1'b1 && d !== 1'b1) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule

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@ -69,6 +69,7 @@ br_gh1256a vvp_tests/br_gh1256a.json
br_gh1256b vvp_tests/br_gh1256b.json
br_gh1258a vvp_tests/br_gh1258a.json
br_gh1258b vvp_tests/br_gh1258b.json
br_gh1286 vvp_tests/br_gh1286.json
ca_time_real vvp_tests/ca_time_real.json
case1 vvp_tests/case1.json
case2 vvp_tests/case2.json

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@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "br_gh1286.v",
"iverilog-args" : [ "-g2009" ]
}