luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vhdlpp: Elaborate if statement condition as bool.

This commit is contained in:
Maciej Suminski 2016-01-08 15:17:17 +01:00
parent b6f1cb221e
commit f52de62729
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
vhdlpp/sequential_elaborate.cc
View File

@ -99,7 +99,7 @@ int IfSequential::elaborate(Entity*ent, ScopeBase*scope)
{ {
int errors = 0; int errors = 0;
errors += cond_->elaborate_expr(ent, scope, 0); errors += cond_->elaborate_expr(ent, scope, &type_BOOLEAN);
for (list<SequentialStmt*>::iterator cur = if_.begin() for (list<SequentialStmt*>::iterator cur = if_.begin()
; cur != if_.end() ; ++cur) { ; cur != if_.end() ; ++cur) {
@ -123,7 +123,7 @@ int IfSequential::Elsif::elaborate(Entity*ent, ScopeBase*scope)
{ {
int errors = 0; int errors = 0;
errors += cond_->elaborate_expr(ent, scope, 0); errors += cond_->elaborate_expr(ent, scope, &type_BOOLEAN);
for (list<SequentialStmt*>::iterator cur = if_.begin() for (list<SequentialStmt*>::iterator cur = if_.begin()
; cur != if_.end() ; ++cur) { ; cur != if_.end() ; ++cur) {