Add an LPM device type.

tgt-fpga/.cvsignore

@@ -2,6 +2,7 @@ configure
 config.cache
 config.log
 config.status
+autom4te.cache
 Makefile
 fpga.tgt
 dep

tgt-fpga/Makefile.in

@@ -17,7 +17,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.11 2003/07/02 00:27:24 steve Exp $"
+#ident "$Id: Makefile.in,v 1.12 2003/08/07 04:04:01 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -53,7 +53,7 @@ dep:
 	$(CC) -Wall @ident_support@ -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
 	mv $*.d dep
 
-D = d-generic.o d-generic-edif.o d-virtex.o d-virtex2.o
+D = d-generic.o d-generic-edif.o d-lpm.o d-virtex.o d-virtex2.o
 O = edif.o fpga.o gates.o mangle.o tables.o generic.o xilinx.o $D
 
 ifeq (@WIN32@,yes)

tgt-fpga/d-lpm.c

@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2003 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ifdef HAVE_CVS_IDENT
+#ident "$Id: d-lpm.c,v 1.1 2003/08/07 04:04:01 steve Exp $"
+#endif
+
+/*
+ * This is the driver for a purely generic LPM module writer. This
+ * uses LPM version 2 1 0 devices, without particularly considering
+ * the target technology.
+ *
+ * The LPM standard is EIA-IS/103-A  October 1996
+ * The output is EDIF 2 0 0 format.
+ */
+
+# include  "device.h"
+# include  "fpga_priv.h"
+# include  "edif.h"
+# include  "generic.h"
+# include  <string.h>
+# include  <assert.h>
+
+static edif_cell_t lpm_cell_buf(void)
+{
+      static edif_cell_t tmp = 0;
+
+      if (tmp != 0)
+	    return tmp;
+
+      tmp = edif_xcell_create(xlib, "BUF", 2);
+      edif_cell_portconfig(tmp, 0, "Result", IVL_SIP_OUTPUT);
+      edif_cell_portconfig(tmp, 1, "Data",   IVL_SIP_INPUT);
+
+      edif_cell_pstring(tmp,  "LPM_TYPE",  "LPM_OR");
+      edif_cell_pinteger(tmp, "LPM_Width", 1);
+      edif_cell_pinteger(tmp, "LPM_Size",  1);
+      return tmp;
+}
+
+static edif_cell_t lpm_cell_inv(void)
+{
+      static edif_cell_t tmp = 0;
+
+      if (tmp != 0)
+	    return tmp;
+
+      tmp = edif_xcell_create(xlib, "INV", 2);
+      edif_cell_portconfig(tmp, 0, "Result", IVL_SIP_OUTPUT);
+      edif_cell_portconfig(tmp, 1, "Data",   IVL_SIP_INPUT);
+
+      edif_cell_pstring(tmp,  "LPM_TYPE",  "LPM_INV");
+      edif_cell_pinteger(tmp, "LPM_Width", 1);
+      edif_cell_pinteger(tmp, "LPM_Size",  1);
+      return tmp;
+}
+
+static void lpm_show_header(ivl_design_t des)
+{
+      unsigned idx;
+      ivl_scope_t root = ivl_design_root(des);
+      unsigned sig_cnt = ivl_scope_sigs(root);
+      unsigned nports = 0, pidx;
+
+	/* Count the ports I'm going to use. */
+      for (idx = 0 ;  idx < sig_cnt ;  idx += 1) {
+	    ivl_signal_t sig = ivl_scope_sig(root, idx);
+
+	    if (ivl_signal_port(sig) == IVL_SIP_NONE)
+		  continue;
+
+	    if (ivl_signal_attr(sig, "PAD") != 0)
+		  continue;
+
+	    nports += ivl_signal_pins(sig);
+      }
+
+	/* Create the base edf object. */
+      edf = edif_create(ivl_scope_basename(root), nports);
+
+
+      pidx = 0;
+      for (idx = 0 ;  idx < sig_cnt ;  idx += 1) {
+	    edif_joint_t jnt;
+	    ivl_signal_t sig = ivl_scope_sig(root, idx);
+
+	    if (ivl_signal_port(sig) == IVL_SIP_NONE)
+		  continue;
+
+	    if (ivl_signal_attr(sig, "PAD") != 0)
+		  continue;
+
+	    if (ivl_signal_pins(sig) == 1) {
+		  edif_portconfig(edf, pidx, ivl_signal_basename(sig),
+				  ivl_signal_port(sig));
+
+		  assert(ivl_signal_pins(sig) == 1);
+		  jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
+		  edif_port_to_joint(jnt, edf, pidx);
+
+	    } else {
+		  const char*name = ivl_signal_basename(sig);
+		  ivl_signal_port_t dir = ivl_signal_port(sig);
+		  char buf[128];
+		  unsigned bit;
+		  for (bit = 0 ;  bit < ivl_signal_pins(sig) ; bit += 1) {
+			const char*tmp;
+			sprintf(buf, "%s[%u]", name, bit);
+			tmp = strdup(buf);
+			edif_portconfig(edf, pidx+bit, tmp, dir);
+
+			jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
+			edif_port_to_joint(jnt, edf, pidx+bit);
+		  }
+	    }
+
+	    pidx += ivl_signal_pins(sig);
+      }
+
+      assert(pidx == nports);
+
+      xlib = edif_xlibrary_create(edf, "LPM_LIBRARY");
+}
+
+static void lpm_show_footer(ivl_design_t des)
+{
+      edif_print(xnf, edf);
+}
+
+static void lpm_logic(ivl_net_logic_t net)
+{
+      edif_cell_t cell;
+      edif_cellref_t ref;
+      edif_joint_t jnt;
+	    
+      switch (ivl_logic_type(net)) {
+
+	  case IVL_LO_BUFZ:
+	  case IVL_LO_BUF:
+	    assert(ivl_logic_pins(net) == 2);
+	    cell = lpm_cell_buf();
+	    ref = edif_cellref_create(edf, cell);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
+	    edif_add_to_joint(jnt, ref, 0);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
+	    edif_add_to_joint(jnt, ref, 1);
+	    break;
+
+	  case IVL_LO_NOT:
+	    assert(ivl_logic_pins(net) == 2);
+	    cell = lpm_cell_inv();
+	    ref = edif_cellref_create(edf, cell);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
+	    edif_add_to_joint(jnt, ref, 0);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
+	    edif_add_to_joint(jnt, ref, 1);
+	    break;
+
+	  default:
+	    fprintf(stderr, "UNSUPPORTED LOGIC TYPE: %u\n",
+		    ivl_logic_type(net));
+	    break;
+      }
+}
+
+static void lpm_show_mux(ivl_lpm_t net)
+{
+      edif_cell_t cell;
+      edif_cellref_t ref;
+      edif_joint_t jnt;
+
+      unsigned idx, rdx;
+
+      char cellname[32];
+
+      unsigned wid_r = ivl_lpm_width(net);
+      unsigned wid_s = ivl_lpm_selects(net);
+      unsigned wid_z = ivl_lpm_size(net);
+
+      sprintf(cellname, "mux%u_%u_%u", wid_r, wid_s, wid_z);
+      cell = edif_xlibrary_findcell(xlib, cellname);
+
+      if (cell == 0) {
+	    unsigned pins = wid_r + wid_s + wid_r*wid_z;
+
+	    cell = edif_xcell_create(xlib, strdup(cellname), pins);
+
+	      /* Make the output ports. */
+	    for (idx = 0 ;  idx < wid_r ;  idx += 1) {
+		  sprintf(cellname, "Result%u", idx);
+		  edif_cell_portconfig(cell, idx, strdup(cellname),
+				       IVL_SIP_OUTPUT);
+	    }
+
+	      /* Make the select ports. */
+	    for (idx = 0 ;  idx < wid_s ;  idx += 1) {
+		  sprintf(cellname, "Sel%u", idx);
+		  edif_cell_portconfig(cell, wid_r+idx, strdup(cellname),
+				       IVL_SIP_INPUT);
+	    }
+
+	    for (idx = 0 ;  idx < wid_z ; idx += 1) {
+		  unsigned base = wid_r + wid_s + wid_r * idx;
+		  unsigned rdx;
+
+		  for (rdx = 0 ;  rdx < wid_r ;  rdx += 1) {
+			sprintf(cellname, "Data%ux%u", idx, rdx);
+			edif_cell_portconfig(cell, base+rdx, strdup(cellname),
+					     IVL_SIP_INPUT);
+		  }
+	    }
+
+	    edif_cell_pstring(cell,  "LPM_Type",   "LPM_MUX");
+	    edif_cell_pinteger(cell, "LPM_Width",  wid_r);
+	    edif_cell_pinteger(cell, "LPM_WidthS", wid_s);
+	    edif_cell_pinteger(cell, "LPM_Size",   wid_z);
+      }
+
+
+      ref = edif_cellref_create(edf, cell);
+
+	/* Connect the pins of the instance to the nexa. Access the
+	   cell pins by name. */
+      for (idx = 0 ;  idx < wid_r ;  idx += 1) {
+	    unsigned pin;
+
+	    sprintf(cellname, "Result%u", idx);
+	    pin = edif_cell_port_byname(cell, cellname);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx));
+	    edif_add_to_joint(jnt, ref, pin);
+      }
+
+      for (idx = 0 ;  idx < wid_s ;  idx += 1) {
+	    unsigned pin;
+
+	    sprintf(cellname, "Sel%u", idx);
+	    pin = edif_cell_port_byname(cell, cellname);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_select(net, idx));
+	    edif_add_to_joint(jnt, ref, pin);
+      }
+
+      for (idx = 0 ;  idx < wid_z ;  idx += 1) {
+	    for (rdx = 0 ;  rdx < wid_r ;  rdx += 1) {
+		  unsigned pin;
+
+		  sprintf(cellname, "Data%ux%u", idx, rdx);
+		  pin = edif_cell_port_byname(cell, cellname);
+
+		  jnt = edif_joint_of_nexus(edf, ivl_lpm_data2(net, idx, rdx));
+		  edif_add_to_joint(jnt, ref, pin);
+	    }
+      }
+}
+
+static void lpm_show_add(ivl_lpm_t net)
+{
+      unsigned idx;
+      char cellname[32];
+      edif_cell_t cell;
+      edif_cellref_t ref;
+      edif_joint_t jnt;
+
+      const char*type = "ADD";
+
+      if (ivl_lpm_type(net) == IVL_LPM_SUB)
+	    type = "SUB";
+
+	/* Find the correct ADD/SUB device in the library, search by
+	   name. If the device is not there, then create it and put it
+	   in the library. */
+      sprintf(cellname, "%s%u", type, ivl_lpm_width(net));
+      cell = edif_xlibrary_findcell(xlib, cellname);
+
+      if (cell == 0) {
+	    unsigned pins = ivl_lpm_width(net) * 3 + 1;
+
+	    cell = edif_xcell_create(xlib, strdup(cellname), pins);
+
+	    for (idx = 0 ;  idx < ivl_lpm_width(net) ;  idx += 1) {
+
+		  sprintf(cellname, "Result%u", idx);
+		  edif_cell_portconfig(cell, idx*3+0, strdup(cellname),
+				       IVL_SIP_OUTPUT);
+
+		  sprintf(cellname, "DataA%u", idx);
+		  edif_cell_portconfig(cell, idx*3+1, strdup(cellname),
+				       IVL_SIP_INPUT);
+
+		  sprintf(cellname, "DataB%u", idx);
+		  edif_cell_portconfig(cell, idx*3+2, strdup(cellname),
+				       IVL_SIP_INPUT);
+	    }
+
+	    edif_cell_portconfig(cell, pins-1, "Cout", IVL_SIP_OUTPUT);
+
+	    edif_cell_pstring(cell,  "LPM_Type",      "LPM_ADD_SUB");
+	    edif_cell_pstring(cell,  "LPM_Direction", type);
+	    edif_cell_pinteger(cell, "LPM_Width",     ivl_lpm_width(net));
+      }
+
+      ref = edif_cellref_create(edf, cell);
+
+	/* Connect the pins of the instance to the nexa. Access the
+	   cell pins by name. */
+      for (idx = 0 ;  idx < ivl_lpm_width(net) ;  idx += 1) {
+	    unsigned pin;
+
+	    sprintf(cellname, "Result%u", idx);
+	    pin = edif_cell_port_byname(cell, cellname);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx));
+	    edif_add_to_joint(jnt, ref, pin);
+
+	    sprintf(cellname, "DataA%u", idx);
+	    pin = edif_cell_port_byname(cell, cellname);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, idx));
+	    edif_add_to_joint(jnt, ref, pin);
+
+	    sprintf(cellname, "DataB%u", idx);
+	    pin = edif_cell_port_byname(cell, cellname);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, idx));
+	    edif_add_to_joint(jnt, ref, pin);
+      }
+}
+
+const struct device_s d_lpm_edif = {
+      lpm_show_header,
+      lpm_show_footer,
+      0,
+      0,
+      lpm_logic,
+      0, /* show_dff */
+      0,
+      0,
+      0,
+      lpm_show_mux, /* show_mux */
+      lpm_show_add, /* show_add */
+      lpm_show_add, /* show_sub */
+      0, /* show_shiftl */
+      0  /* show_shiftr */
+};
+
+/*
+ * $Log: d-lpm.c,v $
+ * Revision 1.1  2003/08/07 04:04:01  steve
+ *  Add an LPM device type.
+ *
+ */
+

tgt-fpga/edif.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: edif.c,v 1.5 2003/06/24 03:55:00 steve Exp $"
+#ident "$Id: edif.c,v 1.6 2003/08/07 04:04:01 steve Exp $"
 #endif
 
 # include  "edif.h"
@@ -28,9 +28,19 @@
 #endif
 # include  <assert.h>
 
+typedef enum property_e {
+      PRP_NONE = 0,
+      PRP_STRING,
+      PRP_INTEGER
+} property_t;
+
 struct cellref_property_ {
       const char*name;
-      const char*value;
+      property_t ptype;
+      union {
+	    const char*str;
+	    long num;
+      } value_;
       struct cellref_property_*next;
 };
 
@@ -74,6 +84,7 @@ struct edif_cell_s {
       unsigned nports;
       struct __cell_port*ports;
 
+      struct cellref_property_*property;
       struct edif_cell_s*next;
 };
 
@@ -152,7 +163,8 @@ void edif_pstring(edif_t edf, const char*name, const char*value)
 {
       struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
       prp->name = name;
-      prp->value = value;
+      prp->ptype = PRP_STRING;
+      prp->value_.str = value;
       prp->next = edf->property;
       edf->property = prp;
 }
@@ -248,6 +260,7 @@ edif_cell_t edif_xcell_create(edif_xlibrary_t xlib, const char*name,
       cell->xlib = xlib;
       cell->nports = nports;
       cell->ports  = calloc(nports, sizeof(struct __cell_port));
+      cell->property = 0;
 
       for (idx = 0 ;  idx < nports ;  idx += 1) {
 	    cell->ports[idx].name = "?";
@@ -279,6 +292,28 @@ unsigned edif_cell_port_byname(edif_cell_t cell, const char*name)
       return idx;
 }
 
+void edif_cell_pstring(edif_cell_t cell, const char*name,
+		       const char*value)
+{
+      struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
+      prp->name  = name;
+      prp->ptype = PRP_STRING;
+      prp->value_.str = value;
+      prp->next  = cell->property;
+      cell->property = prp;
+}
+
+void edif_cell_pinteger(edif_cell_t cell, const char*name,
+			int value)
+{
+      struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
+      prp->name  = name;
+      prp->ptype = PRP_INTEGER;
+      prp->value_.num = value;
+      prp->next  = cell->property;
+      cell->property = prp;
+}
+
 edif_cellref_t edif_cellref_create(edif_t edf, edif_cell_t cell)
 {
       static unsigned u_number = 0;
@@ -303,7 +338,8 @@ void edif_cellref_pstring(edif_cellref_t ref, const char*name,
 {
       struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
       prp->name = name;
-      prp->value = value;
+      prp->ptype = PRP_STRING;
+      prp->value_.str = value;
       prp->next = ref->property;
       ref->property = prp;
 }
@@ -408,6 +444,24 @@ void edif_print(FILE*fd, edif_t edf)
 			fprintf(fd, ")");
 		  }
 
+		  for (prp = cell->property ;  prp ;  prp = prp->next) {
+			fprintf(fd, "\n                (property %s",
+				prp->name);
+
+			switch (prp->ptype) {
+			    case PRP_NONE:
+			      assert(0);
+			    case PRP_STRING:
+			      fprintf(fd, " (string \"%s\")",
+				      prp->value_.str);
+			      break;
+			    case PRP_INTEGER:
+			      fprintf(fd, " (integer %ld)",
+				      prp->value_.num);
+			      break;
+			}
+			fprintf(fd, ")");
+		  }
 		  fprintf(fd, ")))\n");
 	    }
 
@@ -467,8 +521,18 @@ void edif_print(FILE*fd, edif_t edf)
 		    ref->u, ref->cell->name, ref->cell->xlib->name);
 
 	    for (prp = ref->property ;  prp ;  prp = prp->next)
-		  fprintf(fd, " (property %s (string \"%s\"))",
+		  switch (prp->ptype) {
-			  prp->name, prp->value);
+		      case PRP_STRING:
+			fprintf(fd, " (property %s (string \"%s\"))",
+				prp->name, prp->value_.str);
+			break;
+		      case PRP_INTEGER:
+			fprintf(fd, " (property %s (integer %ld))",
+				prp->name, prp->value_.num);
+			break;
+		      case PRP_NONE:
+			assert(0);
+		  }
 
 	    fprintf(fd, ")\n");
       }
@@ -516,8 +580,18 @@ void edif_print(FILE*fd, edif_t edf)
       fprintf(fd, "      (cellRef %s (libraryRef DESIGN))\n", edf->name);
 
       for (prp = edf->property ;  prp ;  prp = prp->next) {
-	    fprintf(fd, "       (property %s (string \"%s\"))\n",
+	    switch (prp->ptype) {
-		    prp->name, prp->value);
+		case PRP_STRING:
+		  fprintf(fd, "       (property %s (string \"%s\"))\n",
+			  prp->name, prp->value_.str);
+		  break;
+		case PRP_INTEGER:
+		  fprintf(fd, "       (property %s (integer %ld))\n",
+			  prp->name, prp->value_.num);
+		  break;
+		case PRP_NONE:
+		  assert(0);
+	    }
       }
 
       fprintf(fd, "    )\n");
@@ -530,6 +604,9 @@ void edif_print(FILE*fd, edif_t edf)
 
 /*
  * $Log: edif.c,v $
+ * Revision 1.6  2003/08/07 04:04:01  steve
+ *  Add an LPM device type.
+ *
  * Revision 1.5  2003/06/24 03:55:00  steve
  *  Add ivl_synthesis_cell support for virtex2.
  *

tgt-fpga/edif.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: edif.h,v 1.4 2003/06/24 03:55:00 steve Exp $"
+#ident "$Id: edif.h,v 1.5 2003/08/07 04:04:01 steve Exp $"
 #endif
 
 # include  <stdio.h>
@@ -172,6 +172,15 @@ extern edif_cell_t edif_xcell_create(edif_xlibrary_t, const char*name,
 extern void edif_cell_portconfig(edif_cell_t cell, unsigned idx,
 				 const char*name, ivl_signal_port_t dir);
 
+/* Cells may have properties attached to them. These properties are
+   included in the library declaration for the cell, instead of the
+   cell instances. */
+extern void edif_cell_pstring(edif_cell_t cell, const char*name,
+			      const char*value);
+extern void edif_cell_pinteger(edif_cell_t cell, const char*name,
+			       int value);
+
+
 /* Ports of cells are normally referenced by their port number. If you
    forget what that number is, this function can look it up by name. */
 extern unsigned edif_cell_port_byname(edif_cell_t cell, const char*name);
@@ -216,6 +225,9 @@ extern void edif_print(FILE*fd, edif_t design);
 
 /*
  * $Log: edif.h,v $
+ * Revision 1.5  2003/08/07 04:04:01  steve
+ *  Add an LPM device type.
+ *
  * Revision 1.4  2003/06/24 03:55:00  steve
  *  Add ivl_synthesis_cell support for virtex2.
  *

tgt-fpga/fpga.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: fpga.c,v 1.8 2003/06/25 01:49:06 steve Exp $"
+#ident "$Id: fpga.c,v 1.9 2003/08/07 04:04:01 steve Exp $"
 #endif
 
 # include "config.h"
@@ -29,7 +29,7 @@
 # include  <ivl_target.h>
 # include  <string.h>
 # include  "fpga_priv.h"
-
+# include  <assert.h>
 
 /* This is the opened xnf file descriptor. It is the output that this
    code generator writes to. */
@@ -83,6 +83,7 @@ static void show_pads(ivl_scope_t scope)
 	    if (pad == 0)
 		  continue;
 
+	    assert(device->show_pad);
 	    device->show_pad(sig, pad);
       }
 }
@@ -111,7 +112,7 @@ int target_design(ivl_design_t des)
 	    arch = 0;
 
       if (arch == 0)
-	    arch = "generic-xnf";
+	    arch = "lpm";
 
       device = device_from_arch(arch);
       if (device == 0) {
@@ -144,6 +145,9 @@ int target_design(ivl_design_t des)
 
 /*
  * $Log: fpga.c,v $
+ * Revision 1.9  2003/08/07 04:04:01  steve
+ *  Add an LPM device type.
+ *
  * Revision 1.8  2003/06/25 01:49:06  steve
  *  Spelling fixes.
  *

tgt-fpga/gates.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: gates.c,v 1.11 2003/06/24 03:55:01 steve Exp $"
+#ident "$Id: gates.c,v 1.12 2003/08/07 04:04:01 steve Exp $"
 #endif
 
 # include  <ivl_target.h>
@@ -37,6 +37,13 @@ static void show_cell_scope(ivl_scope_t scope)
 
 static void show_gate_logic(ivl_net_logic_t net)
 {
+      if (device->show_logic == 0) {
+	    fprintf(stderr, "fpga.tgt: IVL LOGIC not supported"
+		    " by this target.\n");
+	    return;
+      }
+
+      assert(device->show_logic);
       device->show_logic(net);
 }
 
@@ -152,6 +159,9 @@ int show_scope_gates(ivl_scope_t net, void*x)
 
 /*
  * $Log: gates.c,v $
+ * Revision 1.12  2003/08/07 04:04:01  steve
+ *  Add an LPM device type.
+ *
  * Revision 1.11  2003/06/24 03:55:01  steve
  *  Add ivl_synthesis_cell support for virtex2.
  *

tgt-fpga/tables.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: tables.c,v 1.5 2003/03/24 00:47:54 steve Exp $"
+#ident "$Id: tables.c,v 1.6 2003/08/07 04:04:01 steve Exp $"
 #endif
 
 # include  "fpga_priv.h"
@@ -26,6 +26,7 @@
 
 extern const struct device_s d_generic;
 extern const struct device_s d_generic_edif;
+extern const struct device_s d_lpm_edif;
 extern const struct device_s d_virtex_edif;
 extern const struct device_s d_virtex2_edif;
 
@@ -36,6 +37,7 @@ const struct device_table_s {
 } device_table[] = {
       { "generic-edif", &d_generic_edif },
       { "generic-xnf",  &d_generic },
+      { "lpm",          &d_lpm_edif },
       { "virtex",       &d_virtex_edif },
       { "virtex2",      &d_virtex2_edif },
       { 0, 0 }
@@ -58,6 +60,9 @@ device_t device_from_arch(const char*arch)
 
 /*
  * $Log: tables.c,v $
+ * Revision 1.6  2003/08/07 04:04:01  steve
+ *  Add an LPM device type.
+ *
  * Revision 1.5  2003/03/24 00:47:54  steve
  *  Add new virtex2 architecture family, and
  *  also the new edif.h EDIF management functions.