Fix missing outputs from synchronous conditionals to get out from in.
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9468f3d06f
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synth2.cc
18
synth2.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: synth2.cc,v 1.39.2.10 2005/12/14 01:53:39 steve Exp $"
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#ident "$Id: synth2.cc,v 1.39.2.11 2005/12/15 02:38:51 steve Exp $"
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#endif
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# include "config.h"
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@ -561,17 +561,22 @@ bool NetCondit::synth_async(Design*des, NetScope*scope, bool sync_flag,
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/* Connected the clauses to the data inputs of the
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condition. If there are bits unassigned by the case, then
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bind them from the accum bits instead. */
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bind them from the accum bits instead. If the bit is not
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represented in the accum list, but this is a synchronous
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output, then get the bit from the nex_map, which is the
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output held in the DFF. */
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for (unsigned idx = 0 ; idx < asig->pin_count() ; idx += 1) {
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if (asig->pin(idx).is_linked())
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connect(mux->pin_Data(idx, 1), asig->pin(idx));
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else if (accum->pin(idx).is_linked())
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connect(mux->pin_Data(idx, 1), accum->pin(idx));
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else if (sync_flag)
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connect(mux->pin_Data(idx, 1), nex_map->pin(idx));
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else {
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cerr << get_line()
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<< ": error: Condition true clause "
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<< " does not assign expected outputs." << endl;
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<< "does not assign expected outputs." << endl;
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return_flag = false;
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}
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}
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@ -581,10 +586,12 @@ bool NetCondit::synth_async(Design*des, NetScope*scope, bool sync_flag,
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connect(mux->pin_Data(idx, 0), bsig->pin(idx));
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else if (accum->pin(idx).is_linked())
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connect(mux->pin_Data(idx, 0), accum->pin(idx));
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else if (sync_flag)
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connect(mux->pin_Data(idx, 0), nex_map->pin(idx));
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else {
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cerr << get_line()
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<< ": error: Condition false clause "
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<< " does not assign expected outputs." << endl;
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<< "does not assign expected outputs." << endl;
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return_flag = false;
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}
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}
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@ -1238,6 +1245,9 @@ void synth2(Design*des)
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/*
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* $Log: synth2.cc,v $
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* Revision 1.39.2.11 2005/12/15 02:38:51 steve
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* Fix missing outputs from synchronous conditionals to get out from in.
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*
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* Revision 1.39.2.10 2005/12/14 01:53:39 steve
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* Handle both asynchronous set and reset.
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*
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