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Allow for implicit case default in synchronous processes.

This commit is contained in:
steve 2006-01-01 01:30:39 +00:00
parent 3131fa68b7
commit f28aa11936
1 changed files with 37 additions and 19 deletions
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56
synth2.cc
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2002-2003 Stephen Williams (steve@icarus.com) * Copyright (c) 2002-2006 Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU * and/or modify it in source code form under the terms of the GNU
@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: synth2.cc,v 1.39.2.13 2005/12/31 04:28:15 steve Exp $" #ident "$Id: synth2.cc,v 1.39.2.14 2006/01/01 01:30:39 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -400,31 +400,46 @@ bool NetCase::synth_async(Design*des, NetScope*scope, bool sync_flag,
default_sig = sig; default_sig = sig;
} }
if (statement_map[item] == 0) { if (statement_map[item] == 0 && !sync_flag) {
/* Missing case and no default; this could still be /* Missing case and no default; this could still be
* synthesizable with synchronous logic, but not here. */ * synthesizable with synchronous logic, but not here. */
cerr << get_line() cerr << get_line()
<< ": error: Incomplete case statement" << ": error: Incomplete case"
<< " is missing a default case." << endl; << " in asynchronous process"
<< " needs a default case." << endl;
return_flag = false; return_flag = false;
continue; continue;
} }
/* Synthesize this case. The synth_async will connect if (statement_map[item] == 0) {
all the output bits it knows how to the sig net. */
statement_map[item]->synth_async(des, scope, sync_flag,
nex_map, sig, accum);
for (unsigned idx = 0 ; idx < mux->width() ; idx += 1) { /* If this is an unspecified case, then get the
if (sig->pin(idx).is_linked()) input from the synchronous output. Note that we
connect(mux->pin_Data(idx, item), sig->pin(idx)); know by design that there is no relevent
else if (accum->pin(idx).is_linked()) default or accum input to use here, as those
connect(mux->pin_Data(idx, item), accum->pin(idx)); cases are handled above. */
else {
cerr << get_line() for (unsigned idx=0; idx < mux->width(); idx += 1)
<< ": error: case " << item << " statement " connect(mux->pin_Data(idx,item), nex_map->pin(idx));
<< " does not assign expected outputs." << endl;
return_flag = false; } else {
/* Synthesize this specified case. The synth_async will
connect all the output bits it knows how to the
sig net. */
statement_map[item]->synth_async(des, scope, sync_flag,
nex_map, sig, accum);
for (unsigned idx = 0 ; idx < mux->width() ; idx += 1) {
if (sig->pin(idx).is_linked())
connect(mux->pin_Data(idx, item), sig->pin(idx));
else if (accum->pin(idx).is_linked())
connect(mux->pin_Data(idx, item), accum->pin(idx));
else {
cerr << get_line()
<< ": error: case " << item << " statement "
<< " does not assign expected outputs." << endl;
return_flag = false;
}
} }
} }
} }
@ -1354,6 +1369,9 @@ void synth2(Design*des)
/* /*
* $Log: synth2.cc,v $ * $Log: synth2.cc,v $
* Revision 1.39.2.14 2006/01/01 01:30:39 steve
* Allow for implicit case default in synchronous processes.
*
* Revision 1.39.2.13 2005/12/31 04:28:15 steve * Revision 1.39.2.13 2005/12/31 04:28:15 steve
* Fix crashes caused bu synthesis of sqrt32.v. * Fix crashes caused bu synthesis of sqrt32.v.
* *