luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix signedness of non-ANSI port declarations (issue #540). 

For non-ANSI port declarations that have both a port declaration and
a corresponding variable declaration, the signed attribute may be
attached to either the port declaration or the variable declaration,
or both declarations.
This commit is contained in:
Martin Whitaker 2021-09-10 23:09:03 +01:00
parent 7ee7a48310
commit ef01dd1e81
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
PWire.cc
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 1999-2019 Stephen Williams (steve@icarus.com) * Copyright (c) 1999-2021 Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU * and/or modify it in source code form under the terms of the GNU
@ -132,7 +132,13 @@ ivl_variable_type_t PWire::get_data_type() const
void PWire::set_signed(bool flag) void PWire::set_signed(bool flag)
{ {
signed_ = flag; // For a non-ANSI style port declaration where the data type is
// specified in a corresponding variable declaration, the signed
// attribute may be attached to either the port declaration or to
// the variable declaration (IEEE 1364-2005 section 12.3.3). The
// signal is signed if either the port or the variable is signed.
// Handle that here.
signed_ = signed_ || flag;
} }
bool PWire::get_signed() const bool PWire::get_signed() const